Peephole optimizationPeephole optimization is an optimization technique performed on a small set of compiler-generated instructions; the small set is known as the peephole or window. Peephole optimization involves changing the small set of instructions to an equivalent set that has better performance.
Logique polyvalenteLes logiques polyvalentes (ou multivalentes, ou multivaluées) sont des alternatives à la logique classique aristotélicienne, bivalente, dans laquelle toute proposition doit être soit vraie soit fausse. Elles sont apparues à partir des années 1920, surtout à la suite des travaux du logicien polonais Jan Łukasiewicz. Elles sont principalement étudiées au niveau du seul calcul propositionnel et peu au niveau du calcul des prédicats.
High-level synthesisHigh-level synthesis (HLS), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. Synthesis begins with a high-level specification of the problem, where behavior is generally decoupled from low-level circuit mechanics such as clock-level timing.
Optimisation de boucleIn compiler theory, loop optimization is the process of increasing execution speed and reducing the overheads associated with loops. It plays an important role in improving cache performance and making effective use of parallel processing capabilities. Most execution time of a scientific program is spent on loops; as such, many compiler optimization techniques have been developed to make them faster. Since instructions inside loops can be executed repeatedly, it is frequently not possible to give a bound on the number of instruction executions that will be impacted by a loop optimization.
Programmation logiqueLa programmation logique est une forme de programmation qui définit les applications à l'aide : d'une base de faits : ensemble de faits élémentaires concernant le domaine visé par l'application, d'une base de règles : règles de logique associant des conséquences plus ou moins directes à ces faits, d'un moteur d'inférence (ou démonstrateur de théorème ) : exploite ces faits et ces règles en réaction à une question ou requête. Cette approche se révèle beaucoup plus souple que la définition d'une succession d'instructions que l'ordinateur exécuterait.
Circuits statiques et dynamiquesIn integrated circuit design, dynamic logic (or sometimes clocked logic) is a design methodology in combinational logic circuits, particularly those implemented in metal–oxide–semiconductor (MOS) technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances. It was popular in the 1970s and has seen a recent resurgence in the design of high-speed digital electronics, particularly central processing units (CPUs).
Interprocedural optimizationInterprocedural optimization (IPO) is a collection of compiler techniques used in computer programming to improve performance in programs containing many frequently used functions of small or medium length. IPO differs from other compiler optimizations by analyzing the entire program as opposed to a single function or block of code. IPO seeks to reduce or eliminate duplicate calculations and inefficient use of memory and to simplify iterative sequences such as loops.
Register Transfer LevelRegister Transfer Level (RTL) est une méthode de description des architectures microélectroniques. Dans la conception RTL, le comportement d'un circuit est défini en termes d'envois de signaux ou de transferts de données entre registres, et les opérations logiques effectuées sur ces signaux. Le RTL est utilisé dans les langages de description matérielle (HDL) comme Verilog et VHDL pour créer des représentations d'un circuit à haut niveau, à partir duquel les représentations à plus bas niveau et le câblage réel peuvent être dérivés.
Espresso heuristic logic minimizerThe ESPRESSO logic minimizer is a computer program using heuristic and specific algorithms for efficiently reducing the complexity of digital logic gate circuits. ESPRESSO-I was originally developed at IBM by Robert K. Brayton et al. in 1982. and improved as ESPRESSO-II in 1984. Richard L. Rudell later published the variant ESPRESSO-MV in 1986 and ESPRESSO-EXACT in 1987. Espresso has inspired many derivatives. Electronic devices are composed of numerous blocks of digital circuits, the combination of which performs the required task.
Knowledge representation and reasoningKnowledge representation and reasoning (KRR, KR&R, KR2) is the field of artificial intelligence (AI) dedicated to representing information about the world in a form that a computer system can use to solve complex tasks such as diagnosing a medical condition or having a dialog in a natural language. Knowledge representation incorporates findings from psychology about how humans solve problems and represent knowledge in order to design formalisms that will make complex systems easier to design and build.
