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From LDPC Block to LDPC Convolutional Codes: Capacity, Stability, and Universality

Publications associées (290)

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A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction

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Scratchpad memory (SPM) is widely used in modern embedded processors to overcome the limitations of cache memory. The high vulnerability of SPM to soft errors, however, limits its usage in safety-critical applications. This paper proposes an efficient faul ...

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The advent of wireless communication technologies has created a paradigm shift in the accessibility of communication. With it has come an increased demand for throughput, a trend that is likely to increase further in the future. A key aspect of these chall ...

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Secure network coding assumes that the underlying network channels are error-free; thus, if our channels introduce errors, we need to first apply a channel code to correct them, and then build security on top of the resulting error-free network. In this pa ...

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Polar codes are introduced for discrete memoryless broadcast channels. For m-user deterministic broadcast channels, polarization is applied to map uniformly random message bits from m-independent messages to one codeword while satisfying broadcast constrai ...

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Asynchronous Decoding of LDPC Codes over BEC

Amin Karbasi, Amir Hesam Salavati, Saeid Haghighatshoar

LDPC codes are typically decoded by running a synchronous message passing algorithm over the corresponding bipartite factor graph (made of variable and check nodes). More specifically, each synchronous round consists of 1) updating all variable nodes based ...

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Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder

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The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated w ...

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