Characterization and Modeling of Total Ionizing Dose Effects on Nanoscale MOSFETs for Particle Physics Experiments

Total ionizing radiation compromises electrical characteristics of microelectronic devices and even causes functional failures of integrated circuits. It has been identified as a potential threat to electronic components, especially those in high-energy physics experiments, space and avionic systems, and nuclear power plants. Among all harsh radiation environments, the future High Luminosity Large Hadron Collider (HL-LHC) at European Organization for Nuclear Research (CERN), is expected to have by far the highest levels of total ionizing dose (TID) with a peak of 1 Grad in the innermost electronics. Also, the number of pileup events per bunch crossing can reach up to 200, challenging trigger and data acquisition systems of its particle experiments. To reach long-term reliable operation, the HL-LHC will require innovative detecting and tracking systems with a higher level of granularity and bandwidth as well as robust radiation-tolerant front-end electronics.

Complementary metal-oxide-semiconductor (CMOS) scaling allows extended circuit functionality and enhanced computing power. It also improves the TID tolerance of MOS field-effect transistors (MOSFETs) with relieved charge trapping related to ultrascaled gate dielectrics. To evaluate the potential use of highly scaled devices in the HL-LHC and eventually support circuit design for radiation-tolerant applications, this thesis characterizes and models the effects of TID up to 1 Grad on a commercial 28-nm bulk CMOS process. The characterization part focuses on evaluating measurable radiation effects and identifying dominant physical mechanisms. The modeling part aims at improving the understanding of the observed radiation effects and developing a design-oriented compact model for comprehensively accounting for them.

Under various bias and temperature conditions, devices are irradiated, annealed, and tested after each irradiation and annealing step. Most of them demonstrate slight parametric shifts, confirming the very high TID tolerance of ultrathin gate dielectrics. TID-induced degradation in this technology primarily depends on charge trapping related to thick shallow trench isolation (STI) oxides. STI-trapped positive charges in nMOSFETs open parasitic channels along STI sidewalls and cause a significant increase in the drain leakage current, which however almost disappears after high-temperature annealing. STI-related charge trapping can even be strong enough to influence the central part of a narrow channel and is seen seriously degrading the performance of narrow-channel MOSFETs, which however can be relieved by shortening the channel.

The TID-induced parasitic leakage current of nMOSFETs is modeled via a gateless charge-controlled transistor. To model the effects of TID on inversion operation, a generalized Enz-Krummenacher-Vittoz (EKV) charge-based MOSFET model is developed through the incorporation of radiation-induced trapped charges into the original EKV MOSFET model. Despite a small number of parameters, this model demonstrates an excellent match with measurement results over a wide range of device operation. The effects of TID on MOSFET characteristics are efficiently described by those few model parameters. This newly-developed radiation-aware EKV MOSFET model also demonstrates a width dependence of TID effects on 28-nm bulk MOSFETs, which can be explored for the model extension to a broad range of device dimensions even for a continuous range of TID levels.