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Successive Refinement to Caching for Dynamic Requests

Publications associées (40)

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In this paper, we consider a cache aided network in which each user is assumed to have individual caches, while upon users’ requests, an update message is sent through a common link to all users. First, we formulate a general information theoretic setting ...

Institute of Electrical and Electronics Engineers2017

Information Theoretic Caching: The Multi-User Case

Michael Christoph Gastpar, Sung Hoon Lim, Chien-Yi Wang

In this paper, we present information theoretic inner and outer bounds on the fundamental tradeoff between cache memory size and update rate in a multi-user cache network. Each user is assumed to have individual caches, while upon users’ requests, an updat ...

Ieee2016

Information-Theoretic Caching: Sequential Coding for Computing

Michael Christoph Gastpar, Sung Hoon Lim, Chien-Yi Wang

Under the paradigm of caching, partial data are delivered before the actual requests of users are known. In this paper, this problem is modeled as a canonical distributed source coding problem with side information, where the side information represents th ...

Institute of Electrical and Electronics Engineers2016

A New Converse Bound for Coded Caching

Michael Christoph Gastpar, Sung Hoon Lim, Chien-Yi Wang

An information-theoretic lower bound is developed for the caching system studied by Maddah-Ali and Niesen. By comparing the proposed lower bound with the decentralized coded caching scheme of Maddah-Ali and Niesen, the optimal memory--rate tradeoff is char ...

2016

Information-Theoretic Caching

Michael Christoph Gastpar, Sung Hoon Lim, Chien-Yi Wang

Motivated by the caching problem introduced by Maddah-Ali and Niesen, a problem of distributed source coding with side information is formulated, which captures a distinct interesting aspect of caching. For the single-user case, a single-letter characteriz ...

2015

A Primer on Hardware Prefetching

Babak Falsafi

Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution r ...

Morgan & Claypool2014

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Way Stealing is a simple architectural modification to a cache-based processor that increases the data bandwidth to and from application-specific instruction set extensions (ISEs), which increase performance and reduce energy consumption. Way Stealing offe ...

Institute of Electrical and Electronics Engineers2014

When it comes to performance, embedded systems share many problems with their higher-end counterparts. The growing gap between top processor frequency and memory access speed, the memory wall, is one such problem. Driven, in part, by low energy consumption ...

EPFL2010

Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

Increases in on-chip communication delay and the large working sets of server and scientific workloads complicate the design of the on-chip last- level cache for multicore processors. The large working sets favor a shared cache design that maximizes the ag ...

2009

Way Stealing: Cache-assisted Automatic Instruction Set Extensions

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Philip Brisk

This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Extensions (ISEs). Way Stealing provides more bandwidth to the ISE-logic than the ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009