8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment

Digital PLLs are popular for on-chip clock generation due to their small size and technology portability. Variability tolerance is a key design challenge when designing such PLLs in an advanced CMOS technology. Environmental variations, such as mismatch, process, supply voltage, and temperature (PVT) perturb device characteristics and result in performance changes, such as DCO gain and noise. Another consideration is the wide range of operating modes in which modern digital circuits (e.g., processors) operate. For instance, a clock generator for a processor may produce a range of frequencies from tens of MHz to several GHz depending on required processor performance. In low-frequency mode, the power consumption is more pronounced than the noise. Therefore, we seek to design a PLL that is both insensitive to environmental variations, as well as reconfigurable to changing noise and power specifications.