Publications associées à Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

Marco Mattavelli, Christophe Lucarz, Ghislain Roquier

Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++). As we are entering in the multicore era, sequential programs are no longer ...

2010

High-Performance Modular Multiplication on the Cell Processor

Joppe Willem Bos

This paper presents software implementation speed records for modular multiplication arithmetic on the synergistic processing elements of the Cell broadband engine (Cell) architecture. The focus is on moduli which are of special interest in elliptic curve ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

High-Performance Modular Multiplication on the Cell Processor

Joppe Willem Bos

Springer Berlin Heidelberg2010

Sound Speed Estimation Using Wave-based Ultrasound Tomography: Theory and GPU Implementation

Martin Vetterli, Olivier Roy, Ali Hormati, Ivana Jovanovic, Reza Parhizkar

We present preliminary results obtained using a time domain wave-based reconstruction algorithm for an ultrasound transmission tomography scanner with a circular geometry. While a comprehensive description of this type of algorithm has already been given e ...

Spie-Int Soc Optical Engineering, Po Box 10, Bellingham, Wa 98227-0010 Usa2010

Montgomery Multiplication on the Cell

Joppe Willem Bos, Marcelo Kaihara

A technique to speed up Montgomery multiplication targeted at the Synergistic Processor Elements (SPE) of the Cell Broadband Engine is proposed. The technique consists of splitting a number into four consecutive parts. These parts are placed one by one in ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

ECC2K-130 on Cell CPUs

Joppe Willem Bos, Thorsten Kleinjung

This paper describes an implementation of Pollard's rho algorithm to compute the elliptic curve discrete logarithm for the Synergistic Processor Elements of the Cell Broadband Engine Architecture. Our implementation targets the elliptic curve discrete loga ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Compilation for Delay Impact Minimization in VLIW Embedded Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Tomorrow’s embedded devices need to run high resolution multimedia as well as need to support multistandard wireless systems which require an enormous computational complexity with a very low energy consumption and very high performance constraints. In thi ...

IEEE Press2006

Processor Enhancements for Media Streaming Applications

Pierre Vandergheynst, Sébastien Bilavarn

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several ...

Springer, Kluwer Academic Publishers2005

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Graph Chatbot

Chattez avec Graph Search

High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

High-Performance Modular Multiplication on the Cell Processor

High-Performance Modular Multiplication on the Cell Processor

Sound Speed Estimation Using Wave-based Ultrasound Tomography: Theory and GPU Implementation

Montgomery Multiplication on the Cell

ECC2K-130 on Cell CPUs

Flexible Hardware Acceleration for Instruction-Grain Lifeguards

Compilation for Delay Impact Minimization in VLIW Embedded Systems

Processor Enhancements for Media Streaming Applications

Adding limited reconfigurability to superscalar processors

High-Performance Modular Multiplication on the Cell Processor

High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

Flexible Hardware Acceleration for Instruction-Grain Lifeguards

Montgomery Multiplication on the Cell

Adding limited reconfigurability to superscalar processors

Processor Enhancements for Media Streaming Applications

High-Performance Modular Multiplication on the Cell Processor

Compilation for Delay Impact Minimization in VLIW Embedded Systems

Sound Speed Estimation Using Wave-based Ultrasound Tomography: Theory and GPU Implementation

ECC2K-130 on Cell CPUs