Automating the Design of Programmable Interconnect for Reconfigurable Architectures
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This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers very high noise immunity due to the differential ope ...
This paper presents a regular layout fabric made of via-programmable MCML universal logic cells for structured ASIC applications and the associated design flow. The proposed structured ASIC fabric offers high speed operation, very high noise immunity, as w ...
This thesis is at the crossroad between Natural Language Processing (NLP) and digital circuit design. It aims at delivering a custom hardware coprocessor for accelerating natural language parsing. The coprocessor has to parse real-life natural language and ...
Specification, simulation and optimization of sensors and actuators can be done through behavioral modeling using analog hardware description languages. The resulting models can be used in conjunction with models of the associated electronics to simulate a ...
Field programmable gate arrays (FPGA) are a recently developed family of programmable circuits. Like mask programmable gate arrays (MPGA), FPGAs implement thousands of logic gates. But, unlike MPGAs, a user can program an FPGA design as traditional program ...
A new top-down design flow (RTL-to-GDSII) is proposed for achieving high-performance and noiseimmune designs consisting of differential logic blocks. The differential building blocks are based on the currentmode logic (CML), which offers true differentiali ...
Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control units, must include design optimization procedures to yield area-effective circuits. We model sequential functions as deterministic synchronous Finite State Ma ...
