Publications associées à Digital One-Shot Charge-balancing Method for Implantable Current-Mode Electrical Stimulation

Chattez avec Graph Search

Posez n’importe quelle question sur les cours, conférences, exercices, recherches, actualités, etc. de l’EPFL ou essayez les exemples de questions ci-dessous.

AVERTISSEMENT : Le chatbot Graph n'est pas programmé pour fournir des réponses explicites ou catégoriques à vos questions. Il transforme plutôt vos questions en demandes API qui sont distribuées aux différents services informatiques officiellement administrés par l'EPFL. Son but est uniquement de collecter et de recommander des références pertinentes à des contenus que vous pouvez explorer pour vous aider à répondre à vos questions.

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

Seyed Armin Tajalli, Yusuf Leblebici

A current-mode

\Delta\Sigma

analog-to-digital data converter (ADC) for biomedical readout front-end systems is being presented. The core of this circuit is a current-controlled ring oscillator (CCO) whose oscillation frequency is proportional to the inpu ...

2010

Digital One-Shot Charge-balancing Method for Implantable Current-Mode Electrical Stimulation

Graph Chatbot

Chattez avec Graph Search

Modular DC/DC Converter for DC Distribution and Collection Networks

Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

Optimizing a Battery Energy Storage System for Frequency Control Application in an Isolated Power System

An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters

Multi-unit global energy management and optimization for network-on-chip applications

An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth

Low-Power Adaptive Bias/Clock Generator Using 0.18um CMOS Technology for Multi-Core Continuous Voltage and Frequency Scaling

Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor

Modular DC/DC Converter for DC Distribution and Collection Networks

Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies

Multi-unit global energy management and optimization for network-on-chip applications

A 9 pW/Hz Adjustable Clock Generator with 3-Decade Tuning Range for Dynamic Power Management in Subthreshold SCL Systems

Subthreshold Current-Mode Delta-Sigma Quantizer with 3-Decade Scalable Sampling Rate and pico-Ampere Range Resolution

Optimizing a Battery Energy Storage System for Frequency Control Application in an Isolated Power System

An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters

An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth

Low-Power Adaptive Bias/Clock Generator Using 0.18um CMOS Technology for Multi-Core Continuous Voltage and Frequency Scaling

Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor