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Spyder

Publications associées (138)

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System for generating computer processor

A method and apparatus to produce a net list of gates and Flip-Flops for one algorithm in order to find the best compromise between power consumption, speed and silicon surface by using a two step process. First the algorithm is written for a processor tha ...

2010

ParaLog: enabling and accelerating online parallel monitoring of multithreaded applications

Babak Falsafi, Evangelos Vlachos

Instruction-grain lifeguards monitor the events of a running application at the level of individual instructions in order to identify and help mitigate application bugs and security exploits. Because such lifeguards impose a 10-100X slowdown on existing pl ...

ACM Press2010

A Tighter Analysis of Work Stealing

Nicolas Gabriel Gast, Denis Trystram

Classical list scheduling is a very popular and efficient technique for scheduling jobs in parallel platforms. However, with the increasing number of processors, the cost for managing a single centralized list becomes prohibitive. The objective of this wor ...

Springer Berlin Heidelberg2010

Recent Developments in Flow Boiling and Two-Phase Flow in Small Channels and Microchannels

John Richard Thome, Andrea Cioncolini

Microscale two-phase flow is at present one of the hottest topics of heat transfer research, both in academia and in the industry. The miniaturization of two-phase flow systems, which has led to numerous experimental and theoretical challenges not yet comp ...

Taylor & Francis2010

ECC2K-130 on Cell CPUs

Joppe Willem Bos, Thorsten Kleinjung

This paper describes an implementation of Pollard's rho algorithm to compute the elliptic curve discrete logarithm for the Synergistic Processor Elements of the Cell Broadband Engine Architecture. Our implementation targets the elliptic curve discrete loga ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

A hardware-software codesign framework for cellular computing

Pierre-André Mudry

Until recently, the ever-increasing demand of computing power has been met on one hand by increasing the operating frequency of processors and on the other hand by designing architectures capable of exploiting parallelism at the instruction level through h ...

EPFL2009

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

David Atienza Alonso, Luca Benini, Srinivasan Murali

Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhanced support for dynamic and partial reconfigurability. Design automation suppor ...

IEEE Press2009

ReSim, a Trace-Driven, Reconfigurable ILP Processor Simulator

Dionysios Pnevmatikatos, Sotiria Fytraki

Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration relies on extensive use of software simulation that when highly accurate is slow. ...

2009

Rapid Design Space visualisation through hardware/software partitioning

Daniel Kuhn

This paper introduces the 3SP Design Space Exploration System. 3SP automatically quantifies acceleration opportunities for programs across a wide range of heterogeneous architectures to allow designers to identify promising implementation platforms before ...

IEEE2009

Parallel eigenvalue reordering in real Schur forms

Daniel Kressner, Bo Kågström

A parallel algorithm for reordering the eigenvalues in the real Schur form of a matrix is presented and discussed. Our novel approach adopts computational windows and delays multiple outside-window updates until each window has been completely reordered lo ...

2009