High tuning range AlSi RF MEMS capacitors fabricated with sacrificial amorphous silicon surface micromachining

This paper reports the fabrication and electrical characterization of high tuning range AlSi RF MEMS capacitors. We present experimental results obtained by a surface micromachining process that uses dry etching of sacrificial amorphous silicon to release Al–1%Si membranes and has a low thermal budget (10,000:1). Single- and double- air-gap MEMS capacitors, as well as some dedicated test structures needed to calibrate the electro-mechanical parameters and explore the reliability of the proposed technology, have been fabricated with the new process. S- parameter measurements from 100 MHz up to 2 GHz have shown a capacitance tuning range higher than 100% with the double-air-gap architecture. The tuning range can be enlarged with a proper DC electrical bias of the capacitor electrodes. Finally, the reported results make the proposed MEMS tuneable capacitor a good candidate for above-IC integration in communications applications.

Above-IC RF MEMS devices for communication applications

Raphaël Fritschi

Wireless communications are showing an explosive growth in emerging consumer and military applications of radiofrequency (RF), microwave, and millimeter-wave circuits and systems. Applications include wireless personal connectivity (Bluetooth), wireless local area networks (WLAN), mobile communication systems (GSM, GPRS, UMTS, CDMA), satellite communications and automotive electronics. Future cell phones and ground communication systems as well as communication satellites will require more and more sophisticated technologies. The increasing demand for size and weight reduction, cost savings, low power consumption, increased frequency and higher functionality and reconfigurability as part of multiband and multistandard operation is necessitating the use of highly integrated RF front-end circuits. Chip scaling has made a major contribution to this goal, but today a situation has been reached where the presence of numerous off-chip passive RF components imposes a critical bottleneck to further integration and miniaturization of wireless transceivers. Microelectromechanical systems (MEMS) technology is a rapidly emerging enabling technology that is intended to replace the discrete passives by their integrated counterparts. In this thesis, an original metal surface micromachining process, which is compatible with CMOS post-processing, for above-IC integration of RF MEMS tunable capacitors and suspended inductors is presented. A detailed study on SF6 inductively coupled plasma (ICP) releasing has been performed in order to ascertain the optimal process parameters. This study has emphasized the fact that temperature plays an important role in this process by limiting silicon dioxide etching. Moreover, the optimized recipe has been found to be independent of the sacrificial layer used (amorphous or polycrystalline silicon) and its thickness. Using this recipe, 15.6 µm/min Si underetch rate with high Si: SiO2 selectivity (> 20000: 1) has been obtained. Single-air-gap and double-air-gap parallel-plate MEMS tunable capacitors have been designed, fabricated and characterized in the pF range, from 1 MHz to 13.5 GHz. It has been shown that an optimized design of the suspended membrane and direct symmetrical current feed at both ports can significantly improve the quality factor and increase the self-resonant frequency, pushing it to 12 GHz and beyond. The maximum capacitance tuning range obtained for a single-air-gap capacitor is 29% for a bias voltage of 20 V. The maximum capacitance tuning range obtained for a double-air-gap capacitor is 207% for a bias voltage of 70 V. The post-processing of X-FAB BiCMOS wafers has been successfully demonstrated to fabricate monolithically integrated VCOs with above-IC MEMS LC tank. Comparing a suspended inductor and the X-FAB inductor with the same design, it has been shown that increasing the thickness of the spiral from 2.3 to 4 µm and having the spiral suspended 3 µm above the passivation layers lead to an improvement factor of 2 for the peak quality factor and a shift of the self-resonant frequency beyond 15 GHz. No significant variation on bipolar and MOS transistors characteristics due to the post-processing has been observed and we conclude that the variation due to post-processing is in the same range as the wafer-to-wafer variation. Based on our metal surface micromachining process, coplanar waveguide (CPW) MEMS shunt capacitive switches and variable true-time delay lines (V-TTDLs) have been designed, fabricated and characterized in the 1 - 20 GHz range. A novel MEMS device architecture: the SG-MOSFET, which combines a solid-state MOS transistor and a metal suspended gate has been proposed as DC current switch. The corresponding fabrication process using polysilicon as a sacrificial layer has been developed to release metal gate suspended over gate oxide by SF6 plasma. Very abrupt current switches have been demonstrated with subthreshold slope better than 10 mV/decade (better than the theoretical solid-state bulk or SOI MOSFET limit of 60 mV/decade) and ultra-low gate leakage (less than 0.001 pA/µm2) due to the air-gap.

EPFL2007

Capacités variables et inductances MEMS RF pour une intégration "Above-IC"

Alexander Mehdaoui

This work was carried out in a collaborative framework between Ecole Polytechnique Fédérale de Lausanne and an industrial partner ST Microelectronics. RF MEMS passives are key devices for the RF front-end in modern transceiver and receiver architectures, offering significant gains in compactness, performance at GHZ frequency and low power consumption. In this context, our work deals with the development of RF MEMS tunable capacitors for above-IC integration, and the co-integration with high-Q MEMS inductors. The possibility to co-integrate L and C functions in the same platform enables the use of this technology in a number of applications such as VCOs and tunable filters. This work addresses the design, simulation and fabrication of tunable capacitors with fragmented metal (AlSi) that are laterally driven by electrothermal and electrostatic actuators. All of MEMS passives components are made with a low-temperature process (above-IC compatible) using polyimide as sacrificial layer, 4 µm AlSi as metal layer and copper. The copper layer is used for a double purpose: (i) to design and fabricate vertically integrated high Q inductors and (ii) to define lateral electrostatic actuators for the MEMS capacitors. To increase the tuning range of MEMS capacitors, we investigate solutions by varying the effective area. First, electro-thermal actuators have been demonstrated for driving suspended electrodes of tunable capacitors such as rotational and lateral actuator. We demonstrated a tuning range of 70% and 25% at 2GHz in case of MEMS capacitors with rotational and lateral actuators, respectively. These solutions evade the pull-in effect but the tuning range is less than 100% and the power consumption is high. For the purpose of power reduction, we develop tunable capacitors with fragmented electrodes that are laterally driven by electrostatic actuator: however, the fabrication process associated with these architectures appears to be very difficult and, finally, it was not possible to show full functional devices. It is worth noting that the design of MEMS capacitors has been supported by electromechanical ANSYS simulations and modeling of the fringing effects, for an optimal device design. In the AlSi layer, we also demonstrate inductors with quality factor in excess of 10 at 2GHz. Basic LC blocks are realized and characterized with a tunable frequency of 25% at 2GHz. Another particular realization are the vertically integrated, thick copper inductors, which have been successfully fabricated and measured (L = 2.5 nH, Q = 15 at 2GHz). Finally, in the same process, we fabricated and characterized WLAN and DCS bandpass filters for a demonstrator dealing with a reconfigurable radio front-end. These components are fabricated with thick copper of 10 µm

EPFL2007

SOI mixed-mode design techniques and case studies

Marija Blagojevic

Since the emergence of Silicon On Insulator (SOI) technology the research activities have been concentrated on a detailed analysis of SOI devices and their use in different application fields (low-voltage, low-power circuits, high temperature electronics, digital circuits, etc.). The present thesis deals with low-voltage, low-power mixed-mode design using a SOI technology. The goal is to establish the concepts that allow one to design SOI mixed-mode circuits, and to apply these concepts to the design of fully depleted (FD) and partially depleted (PD) SOI circuits and systems. Two studies have been realized in the scope of this work: a Hall sensor based microsystem design using an experimental FD SOI technology a DRAM design using capacitor-less 1T floating-body PD SOI memory cells. At the beginning of this thesis, two major types of SOI devices are introduced, namely FD and PD devices. The most important properties of these devices are then presented and compared to those of CMOS bulk devices. A design methodology based on design retargeting from bulk to SOI technology is further proposed. This methodology is developed with the aim of being implemented for the design of FD SOI circuits. It consists in using the same device dimensions and bias currents for the bulk and the corresponding FD SOI design. The analysis performed proves that such an approach permits one to obtain better circuit performances using the FD SOI technology. The EKV model is chosen for Spice simulations. For that purpose the extraction of the EKV intrinsic parameters has been performed for the experimental 0.5 μm FD SOI technology. The EKV model card obtained from transistor measurements is implemented straightforwardly for circuit simulations. The first study presented in this thesis is an FD SOI Hall sensor front-end for energy measurement. The mixed-mode microsystem design is completely based on the proposed design methodology. The system level solutions are also included, such as the spinning-current method that serves for reduction of the offset and low frequency noise of the analog front-end, and a high resolution analog-to-digital conversion technique. The integrated microsystem is entirely functional. Furthermore, according to the existing literature, this integrated circuit is the first microsystem completely realized using FD SOI technology. The overall system error that is obtained is less than 1.5 %. During the second part of this work, a novel sensing scheme that exploits an automatic reference generation based on successive approximations has been developed for the PD SOI capacitor-less 1T DRAM. The 1T DRAM reference current is generated by an adjustable current source. The electrical calibration of the reference current is performed using a digital-to-analog converter and successive approximations algorithm. The proposed scheme is evaluated in a 2 kb test chip. The circuit integrated using PD SOI technology contains a 2 kb 1T memory array, as well as automatic reference generators and peripheral circuits. The automatic reference generator comprises current mode sense amplifier, M/3M converter, and successive approximations register. All blocks implemented in the test chip are described in detail, and PD SOI design issues are discussed. A number of experimental results demonstrate the potential of the PD SOI 1T DRAM for future embedded DRAM applications. The measured retention time under holding conditions is higher than 1s. In the continuous read mode, a few hundreds of the read cycles can be performed without a refresh operation. The test chip has a measured access time of 25 ns with a read cycle time of 70 ns.

EPFL2005

SOI mixed-mode design techniques and case studies

Marija Blagojevic

EPFL2005

Above-IC RF MEMS devices for communication applications

Raphaël Fritschi

EPFL2007

Capacités variables et inductances MEMS RF pour une intégration "Above-IC"

Alexander Mehdaoui

EPFL2007