Publication
A method and apparatus to produce a net list of gates and Flip-Flops for one algorithm in order to find the best compromise between power consumption, speed and silicon surface by using a two step process. First the algorithm is written for a processor that has no restrictions in terms of number and size of register, core, operations set, memory handler and instructions. The program assembly of this processor fits into a two-dimensional table. To increase speed, the tables are configured to place the program operation in as many columns as possible, and to reduce silicon the tables are configured to place operations in a single column with many rows. The second stage consists of converting this virtual processor with its program tables into an HDL file ready for synthesis.