A Reconfigurable Fabric For Accelerating Large-Scale Datacenter Services

Publications associées (31)

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Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Mikhail Asiatici

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Touradj Ebrahimi

Joint Photographic Experts Group (JPEG) XS is a new International Standard from the JPEG Committee (formally known as ISO/International Electrotechnical Commission (IEC) JTC1/SC29/WG1). It defines an interoperable, visually lossless low-latency lightweight ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs

Mirjana Stojilovic, Stefan Nikolic, Morten Borup Petersen

Novel applications have triggered significant changes at the system level of FPGA architecture design, such as the introduction of embedded VLIW processor arrays and hardened NoCs. However, the routing architecture of the soft logic fabric has largely rema ...

2021

Certification of the efficient random number generation technique based on single-photon detector arrays and time-to-digital converters

Edoardo Charbon, Samuel Burri

True random number generators (TRNGs) allow the generation of true random bit sequences, guaranteeing the unpredictability and perfect balancing of the generated values. TRNGs can be realised from the sampling of quantum phenomena, for instance, the detect ...

Wiley2021

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Mirjana Stojilovic, Hossein Asadi, Zeinab Seifoori

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the ...

2021

Design and experimental validation of an FPGA-based PMU simultaneously compliant with P and M performance classes

Mario Paolone, Asja Derviskadic

Low-inertia grids are characterized by high shares of harmonic and inter-harmonic distortion, produced by the inverters that interface non-conventional generation assets to the electrical grid. These interfering tones largely compromise synchrophasor estim ...

Elsevier2020

Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

Simon Nessim Henein, Hubert Pierre-Marie Benoît Schneegans, Ilan Vardi, Mohamed Gamal Abdelrahman Ahmed Zanaty

Binary logic gates are building blocks of computing machines, in particular, electronic computers. One variant is the programable logic gate, also known as the reconfigurable logic gate, in which the logical function implemented can be modified. In this pa ...

2020

Programmable Logic Gates Based On Tunable Multistable Mechanisms

Simon Nessim Henein, Hubert Pierre-Marie Benoît Schneegans, Ilan Vardi, Mohamed Gamal Abdelrahman Ahmed Zanaty

Binary logic operations are the building blocks of computing machines. In this paper, we present a new programmable binary logic gate based on programmable multistable mechanisms (PMM), which are multistable structures whose stability behavior depends on m ...

AMER SOC MECHANICAL ENGINEERS2020

Electromagnetic Time Reversal: Theory, Application to Fault Location in Power Networks and Experimental Validation

Zhaoyang Wang

The time-reversal invariance is readily described and universally embodied in most laws of nature, either in a strict or in a soft sense. Based on this underlying physical principle, time-reversal theory has been theoretically and experimentally studied in ...

EPFL2020

Efficient random number generation techniques for CMOS single-photon avalanche diode array exploiting fast time tagging units

Edoardo Charbon, Samuel Burri

This work presents a technique to produce random bits by exploiting single-photon time of arrival. Two quantum random number generator (QRNG) devices based on the field programmable gate array (FPGA) technology are presented: Randy, which uses one discrete ...

AMER PHYSICAL SOC2020

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JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Touradj Ebrahimi

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Certification of the efficient random number generation technique based on single-photon detector arrays and time-to-digital converters

Edoardo Charbon, Samuel Burri

Wiley2021

Efficient random number generation techniques for CMOS single-photon avalanche diode array exploiting fast time tagging units

Edoardo Charbon, Samuel Burri

AMER PHYSICAL SOC2020