Publication

Analysis of Dampers in Time-Sensitive Networks With Non-Ideal Clocks

Publications associées (27)

Worst-Case Delay Analysis of Time-Sensitive Networks with Network Calculus

Time-sensitive networks, as in the context of IEEE Time-Sensitive Networking (TSN) and IETF Deterministic Networking (DetNet), offer deterministic services with guaranteed bounded latency in order to support safety-critical applications. In this thesis, we ...

EPFL2023

A Network Calculus Analysis of Asynchronous Mechanisms in Time-Sensitive Networks

Ehsan Mohammadpour

Time-sensitive networks provide worst-case guarantees for applications in domains such as the automobile, automation, avionics, and the space industries. A violation of these guarantees can cause considerable financial loss and serious damage to human live ...

EPFL2023

Time vs. Truth: Age-Distortion Tradeoffs and Strategies for Distributed Inference

Yunus Inan

In 1948, Claude Shannon laid the foundations of information theory, which grew out of a study to find the ultimate limits of source compression, and of reliable communication. Since then, information theory has proved itself not only as a quest to find the ...

EPFL2023

Global, Passive Detection of Connection Tampering

Louis-Henri Manuel Jakob Merino

In-network devices around the world monitor and tamper with connections for many reasons, including intrusion prevention, combating spam or phishing, and country-level censorship. Connection tampering seeks to block access to specific domain names or keywo ...

Assoc Computing Machinery2023

Reliable Microsecond-Scale Distributed Computing

Athanasios Xygkis

The landscape of computing is changing, thanks to the advent of modern networking equipment that allows machines to exchange information in as little as one microsecond. Such advancement has enabled microsecond-scale distributed computing, where entire dis ...

EPFL2023

Improved Network-Calculus Nodal Delay-Bounds in Time-Sensitive Networks

Jean-Yves Le Boudec, Eleni Stai, Ehsan Mohammadpour

In time-sensitive networks, bounds on worst-case delays are typically obtained by using network calculus and assuming that flows are constrained by bit-level arrival curves. However, in IEEE TSN or IETF DetNet, source flows are constrained on the number of ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

A Maximum-Likelihood-Based Two-User Receiver for LoRa Chirp Spread-Spectrum Modulation

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Orion Afisiadis, Joachim Tobias Tapparel, Mathieu Pierre Xhonneux

Long Range (LoRa) is an emerging low-power wide-area network technology offering long-range wireless connectivity to Internet of Things (IoT) devices. For energy efficiency reasons, LoRa end nodes implement a nonslotted ALOHA multiple access scheme to tran ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Deficit Round-Robin: A Second Network Calculus Analysis

Jean-Yves Le Boudec, Seyed Mohammadhossein Tabatabaee

Deficit Round-Robin (DRR) is a widespread scheduling algorithm that provides fair queueing with variable-length packets. Bounds on worst-case delays for DRR were found by Boyer et al., who used a rigorous network calculus approach and characterized the ser ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A Low-Complexity LoRa Synchronization Algorithm Robust to Sampling Time Offsets

Orion Afisiadis, Mathieu Pierre Xhonneux

LoRaWAN is nowadays one of the most popular protocols for low-power Internet of Things communications. Although its physical layer, namely LoRa, has been thoroughly studied in the literature, aspects related to the synchronization of LoRa receivers have re ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022