A new interconnect-centric design methodology for high-speed standard cells with crosstalk immunity

One of the biggest challenges that are facing the Very Large Scale Integrated Circuits (VLSI) technologies today is the significant performance gap (3× to 9×) between full custom circuits and Application Specific Integrated Circuits (ASICs) designed in the same process generation. This situation is mainly exacurbated by the lack of suitable design tools and methodologies that can properly take into account the real implications and limitations of very deep submicron (VDSM) and nanometer scale technologies. The limitations are largely related to the signal integrity problems, caused by shrinking feature sizes with each new process. Crosstalk, for example, is one of the major issues because it results in unpredictable circuit behavior. This may cause significant timing variations, if not functional failures. Similarly, device and interconnect parasitics become harder to calculate, especially with irregular layout geometries. Accurate and early prediction of such problems, on the other hand, is virtually not possible with the existing tools. Meanwhile, the custom circuits become less affordable because of the skyrocketing design and manufacturing costs. At this point, the gate-array-like structures are becoming an increasingly popular alternative for rapid, low-cost realization of Integrated Circuits (ICs), filling the gap between Field-Programmable Gate-Arrays (FPGAs) and full-custom ASICs. In this work, the main goal is to provide an interconnect-centric design methodology, for which the underlying thinking is prevention over treatment of all these issues. Therefore, a "recipe" is described on how to early characterize these problems and address them even before they appear later during the implementation process. A simple generic RLCK interconnect model is developed and used to systematically characterize the interconnects of various geometries for delay, power and crosstalk noise. The superior performance of the differential interconnects in comparison to mainstream single-ended lines has lead to addressing the insufficient support of the Electronic Design Automation (EDA) tools for differential signaling. A complete RTL-to-GDSII differential design flow is developed that utilizes the advanced design tools through netlist conversion scripts. The advantages of differential signaling are merged with gate-level regularity in a mask-programmable cell fabric suitable for structured ASIC applications, where the basic building block is a via-programmable universal logic gate in MOS current-mode logic (MCML). The MCML design style offers good speed performance and addresses the noise immunity and crosstalk problems thanks to its differential operation. The unit cell can realize all functions up to 3-input and some of the 4-input and 5-input functions. The implementation of benchmark circuits with the proposed fabric have shown that the associated cost is acceptable when compared to the alternatives (standard-cell ASIC and FPGA). Finally, a novel design methodology is proposed which is based on correct-by-construction approach and is claimed to be a better candidate for future designs in nanometer technologies. The methodology is flexible in the sense that it makes it easier to model and to integrate emerging problems through its simulation based design exploration approach, which, in the scope of this thesis, has been focused on interconnect-related issues only. With case studies it is shown that the number of design flow iterations can be dramatically reduced or even removed by better guiding the physical implementation tools. The results dictate the EDA tools a number of advanced features to offer and/or the designers to more strongly utilize some of the existing tool capabilities, in order to manage the ever increasing design complexity.