Publication

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control

Publications associées (31)

OneFile: A Wait-free Persistent Transactional Memory

A persistent transactional memory (PTM) library provides an easy-to-use interface to programmers for using byte-addressable non-volatile memory (NVM). Previously proposed PTMs have, so far, been blocking. We present OneFile, the first wait-free PTM with in ...

IEEE COMPUTER SOC2019

Learning-Based Hardware Design for Data Acquisition Systems

Cosimo Aprile

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conc ...

EPFL2018

Scalable Synchronization in Shared-Memory Systems: Extrapolating, Adapting, Tuning

Georgios Chatzopoulos

As hardware evolves, so do the needs of applications. To increase the performance of an application, there exist two well-known approaches. These are scaling up an application, using a larger multi-core platform, or scaling out, by distributing work to mul ...

EPFL2018

PowerCool: Simulation of Cooling and Powering of 3D MPSoCs with Integrated Flow Cell Arrays

David Atienza Alonso, Marina Zapater Sancho, Arvind Raj Mahankali Sridhar, Mohamed Mostafa Sabry Aly, Artem Andreev, Bruno Michel

Integrated Flow-Cell Arrays (FCAs) represent a combination of integrated liquid cooling and on-chip power generation, converting chemical energy of the flowing electrolyte solutions to electrical energy. The FCA technology provides a promising way to addre ...

Institute of Electrical and Electronics Engineers2017

A Single-chip 2048x1080 Resolution 32fps 380mW Trinocular Disparity Estimation Processor in 28nm CMOS Technology

Yusuf Leblebici, Abdulkadir Akin, Tugba Demirci, Jonathan Emmanuel D Narinx

This paper presents a single-chip trinocular disparity estimation processor, capable of computing in real-time up to 2048×1080 resolution depth maps at 32fps with up to 256-pixel disparity range using two/three CMOS camera sensors. The most important featu ...

2017

Universally Scalable Concurrent Data Structures

Tudor Alexandru David

The increase in the number of cores in processors has been an important trend over the past decade. In order to be able to efficiently use such architectures, modern software must be scalable: performance should increase proportionally to the number of all ...

EPFL2017

Abstracting Multi-Core Topologies with MCTOP

Rachid Guerraoui, Vasileios Trigonakis, Georgios Chatzopoulos

Portability and efficiency are usually antagonists in multi-core computing. In order to develop efficient code, one needs to take into account the topology of the target multi-cores (e.g., for locality). This clearly hampers code portability. In this paper ...

ACM Press2017

Modeling and optimization of Tunnel-FET architectures exploiting carrier gas dimensionality

Cem Alper

The semiconductor industry, governed by the Moore's law, has achieved the almost unbelievable feat of exponentially increasing performance while lowering the costs for years. The main enabler for this achievement has been the scaling of the CMOS transistor ...

EPFL2017

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Giovanni De Micheli, Luca Benini

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

IEEE2016

MOOLs for MOOCs: A first edX scalable implementation

Denis Gillet, Christophe Salzmann, Yves Henri Philippe Piguet

Deploying remote laboratories at a large scale is the next challenge in remote experimentation. It is referred as Massive Open Online Labs (MOOLs). Being able to sustain a massive number of users accessing a specific resource concurrently is a complex task ...

IEEE2016