Blending Scheduling Barriers: A Hybrid Approach for FPGA-based Post-Quantum Cryptography

FPGAs hold great promises for Post-Quantum Cryptography (PQC) hardware through the adoption of electronic design automation tools such as High-Level Synthesis (HLS). Previous works demonstrated how the combination of pragmas and code refactoring techniques significantly enhances the Quality of Results (QoR) [1]. However, manually modifying the original code presents two notable drawbacks: (1) the performance can be suboptimal, and (2) it is highly prone to interpretation that may compromise functionality. In this work, we leverage innovative HLS techniques and tools based on dynamic scheduling, typically not requiring any code alterations to maximize performance to the greatest extent possible. In particular, we highlight the benefits of combining static and dynamic HLS while designing PQC and how it opens up new challenges for further research in this field.