Laboratoire de nanophotonique et d'optoelectronique integre

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Self-heating analysis of monolithically integrated hybrid III-V/Si PIN diode

Kirsten Emilie Moselund

Self-heating is a crucial effect in integrated nanophotonic devices regarding their power consumption. In this work, we employ coupled 3D thermo-electrical simulations to gain insight into the thermal behavior related to traps in a monolithic InP-InGaAs-InP pin-diode fabricated at IBM-Research Zurich. From transport study, two types of defects are found to be very likely present in the studied device: (i) positive oxide charges close to the interface between III-V materials and top oxide layer and (ii) electron-type traps at the p-InP/i-InGaAs interface. Thermal simulations show that the presence of electron-type traps at the p/i interface enhances the self-heating in the device.

SPIE-INT SOC OPTICAL ENGINEERING2022

Single-Mode Emission in InP Microdisks on Si Using Au Antenna

Kirsten Emilie Moselund

An important building block for on-chip photonic applications is a scaled emitter. Whispering gallery mode cavities based on III-Vs on Si allow for small device footprints and lasing with low thresholds. However, multimodal emission and wavelength stability over a wider range of temperature can be challenging. Here, we explore the use of Au nanorod antennae on InP whispering gallery mode lasers on Si for single-mode emission. We show that by proper choice of the antenna size and positioning, we can suppress the side modes of a cavity and achieve single-mode emission over a wide excitation range. We establish emission trends by varying the size of the antenna and show that the far-field radiation pattern differs significantly for devices with and without antenna. Furthermore, the antenna-induced single-mode emission is dominant from room temperature (300 K) down to 200 K, whereas the cavity without an antenna is multimodal and its dominant emission wavelength is highly temperature-dependent.

AMER CHEMICAL SOC2022

A hybrid III-V tunnel FET and MOSFET technology platform integrated on silicon

Clarissa Convertino, Mihai Adrian Ionescu, Kirsten Emilie Moselund

InGaAs/GaAsSb tunnelling field-effect transistors and InGaAs metal-oxide-semiconductor field-effect transistors can be integrated on the same silicon substrate using conventional CMOS-compatible processes, creating a platform for potential use in low-power logic systems. Tunnel field-effect transistors (TFETs) rely on quantum-mechanical tunnelling and, unlike conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), require less than 60 mV of gate voltage swing to induce one order of magnitude variation in the drain current at ambient temperature. III-V heterostructure TFETs are promising for low-power applications, but are outperformed by MOSFETs in terms of speed and energy efficiency when high performance is required at higher drive voltages. Hybrid technologies-combining both TFETs and MOSFETs-could enable low-power and high-performance applications, but require the co-integration of different materials in a scalable complementary metal-oxide-semiconductor (CMOS) platform. Here, we report a scaled III-V hybrid TFET-MOSFET technology on silicon that achieves a minimum subthreshold slope of 42 mV dec(-1) for TFET devices and 62 mV dec(-1) for MOSFET devices. The InGaAs/GaAsSb TFETs are co-integrated with the InGaAs MOSFETs on the same silicon substrate by means of a CMOS-compatible replacement-metal-gate fabrication flow, allowing independent optimization of both device types.

NATURE RESEARCH2021