Memory Design: Column Multiplexers

In course

Ea exercitation enim amet deserunt elit proident officia sint. Veniam consequat ut consequat minim dolor laborum nisi magna. Deserunt et Lorem commodo enim sit nulla. Cupidatat nostrud occaecat non qui ipsum aliquip sint voluptate elit veniam sit.

Description

This lecture covers the design of memory systems, focusing on column multiplexers with different structures such as single-level, binary tree, and heterogeneous tree. It also discusses the comparison of various column multiplexers and the operation of 3T and 1T DRAM cells, highlighting their differences and advantages.

Instructor

exercitation laboris

Labore ea duis aute elit occaecat officia pariatur. Minim quis irure ipsum exercitation incididunt non adipisicing laborum nostrud est adipisicing. Mollit nostrud veniam et commodo nostrud consequat sint nisi esse.

Official source

https://mediaspace.epfl.ch/media/0_s8762ane

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Ontological neighbourhood

Computer engineering

Hardware engineering: Microprocessors

Computer architecture: Embedded systems

Related lectures (33)