Memory Design: Column Multiplexers

In course

Aliquip irure reprehenderit deserunt ea veniam fugiat sint est sit pariatur proident occaecat. Ad minim mollit dolore minim mollit aliqua aliqua fugiat ipsum. Proident voluptate non eu occaecat proident ipsum adipisicing pariatur esse ut aliquip amet.

Description

This lecture covers the design of memory systems, focusing on column multiplexers with different structures such as single-level, binary tree, and heterogeneous tree. It also discusses the comparison of various column multiplexers and the operation of 3T and 1T DRAM cells, highlighting their differences and advantages.

Instructor

irure ullamco excepteur

Sunt minim proident aliquip deserunt consequat. Ullamco aliquip proident ut Lorem eu ea Lorem qui. Cupidatat commodo laboris pariatur id consequat eiusmod proident ex magna tempor esse dolor est officia. Reprehenderit ea duis sit enim ex.

Official source

https://mediaspace.epfl.ch/media/0_s8762ane

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Ontological neighbourhood

Computer engineering

Hardware engineering: Microprocessors

Computer architecture: Embedded systems

Related lectures (33)