Memory Evolution: From DRAM to SRAM

This lecture discusses the historical increase in memory cells per chip, following Moore's Law, and the exponential development of SRAM and DRAM. It covers the importance of memory in modern IC architectures, the dramatic increase in test time, and the functional models of memory. The lecture delves into the architectures of SRAM and DRAM, the March test notation, and various types of memory faults such as SAF, TF, DRF, CF, and NPSF. It also explores robust path-delay tests, Ippo tests, and the limitations of IDDQ testing, providing insights into advanced testing concepts and the necessity of testing in VLSI systems.