Publication
In this paper, we study the operation of MOS current-mode logic (MCML) gates at lower-than-nominal supply voltages.We show that power can be traded for speed by reducing the supply voltage below the nominal value, while the power-delay product stays nearly constant. We propose a negative bias strategy that enables the gates to operate at maximum speed with a reduced supply voltage, thus achieving a power saving of up to 35% at no cost for speed. Comparison with CMOS logic style are presented for three different technology nodes (0.25\u03bcm, 0.18\u03bcm and 0.13\u03bcm CMOS).
Edoardo Charbon, Claudio Bruschini, Ekin Kizilkan, Pouyan Keshavarzian, Francesco Gramuglia, Myung Jae Lee