Alimentation à découpage

Résumé

Une alimentation à découpage est une alimentation électrique dont la régulation est assurée par des composants électroniques de puissance utilisés en commutation (généralement des transistors). Ce mode de fonctionnement diffère de celui des alimentations linéaires dans lesquelles les composants électroniques sont utilisés en mode linéaire. Une alimentation à découpage de type forward est une alimentation qui transmet instantanément la puissance, alors que celle de type flyback stocke cette énergie sous forme d'énergie magnétique dans une inductance (bobine) et libère ensuite cette énergie dans un circuit dit secondaire. Les alimentations à découpage se sont fortement développées depuis les années 1980 pour pallier les inconvénients des alimentations linéaires : masse élevée (pour le transformateur travaillant à fréquence industrielle de 50 ou 60 Hz) et faible rendement (pour les composants annexes [sauf le transformateur] assurant la régulation de la tension et/ou du courant). Elle

Source officielle

https://fr.wikipedia.org/wiki/Alimentation_%C3%A0_d%C3%A9coupage

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In the last years, static power converters have become widely used in various applications. They can be found in domestic applications, railways, urban and ship transport, and even in several industrial systems. Some of these applications require a high or medium voltage power supply that is easily adjustable while providing good spectral performances. To overcome the maximum blocking voltage limits of the main power switches, multilevel techniques and other new power conversion topologies have been developed. They are series/parallel associations of existing power semiconductors, and allow generating an output voltage with many levels. The number of power semiconductors needed in these topologies increases as the number of levels increases. The power converter circuit becomes more complex and its reliability decreases. This thesis focuses on three-phase multilevel converters based on a series connection of single phase inverters (partial cells) in each phase. It's shown that, feeding partial cells with unequal DC-voltages (asymmetric feeding), increases the number of levels of the generated output voltage without any supplemental complexity to the existing topology. Voltage resolution is increased through interpolating the generated output voltage phasor (three phase voltage in α-β frame). This is achieved by seeking the non redundant switching states of the power switches. The resultant converter can generate a very high resolution voltage phasor up to the possible maximum resolution. This approach is generalized for any number of partial cells. Each partial cell is fed through a three-phase diode rectifier, fed itself through the windings of a multi-secondary low frequency power transformer. From analytical expressions in continuous and discontinuous current conix duction modes, it is shown that, from a supply network point of view, a symmetrical multilevel converter has a smaller total harmonic distortion than an asymmetrical multilevel converter with the same number of partial cells per phase. An asymmetrical multilevel converter is not more interesting than a classical three-phase converter, but its total harmonic distortion is compatible to the recommended IEEE std 519-1992. It is also shown that the advantages of an asymmetric multilevel converter from a load point of view (generation of a high resolution voltage phasor, possibility to choose the number of redundant switching states, reduction of the number of power semiconductors for the same voltage resolution, flexibility for the DC-voltage feeding choice) and the advantages of a symmetrical multilevel converter from a supply network point of view (smaller total harmonic distorsion) can be combined. Simulation results and the experimental test setup showed the reliability of the suggested approach.

EPFL2004

Chargement

The multilevel converters allow generating a voltage waveform whose magnitude and quality are higher than those of conventional converters. They are devoted to medium and high-voltage, high-switching-frequency applications. Among the series connected cell inverters, the symmetrical multilevel inverters are made of identical cells, which topology is generally the H-bridge inverter. This dissertation deals with asymmetrical multilevel converters, which combine high-voltage cells — made of low conduction loss switches — with low-voltage cells — made of low switching loss switches. The different cells play different roles. The goal is to design a converter that has both better energetic efficiency and higher resolution with the same number of cells. This dissertation develops a set of tools that allows synthesizing an asymmetrical multilevel converter. It develops the cell combination rules, which allow defining several cell association classes. The inverter step uniformity condition determines the finesse that can be reached. The optimized modulation condition allows to reduce the highvoltage cell switching frequency without changing the low-voltage cell switching frequency. This property is essential to derive benefit from combining switches of different characteristics. The power balance condition determine how to control the power sharing between the cells. These association classes are different for the single-phase converters and the three-phase converters — without neutral wire. They allow to select a configuration suitable for a given application. Furthermore, several ways that allow improving the inverter resolution are investigated. The modulation is essential to associate a high-quality signal (which will really be delivered to the load by means of the inverter levels) to the reference signal (which should ideally be applied to the load). The modulator evaluation methods are assessed. An approach—based on the modulated signal decomposition in elementary frames—is proposed. The main modulator drawbacks are highlighted. A modulator—which arrange the frames in order—allows to reduce the modulated signal distortion and number of transitions. The specific control methods that allow to minimize the inverter number of switchings are developed. The active power cell supply implies several conversion stages, which decrease the converter energetic efficiency. Some solutions that allow to reduce these losses are proposed. Finally, this dissertation attempts to determine, which are the more interesting solutions, depending on the application.

EPFL2005

Chargement

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device performance. As the density of number of devices increases a rise in dynamic and especially static power dissipation is ever more present, making this the biggest issue in microelectronics today. Planar silicon devices are therefore already being replaced by multiple-gate architectures and will be replaced by new channel materials and new switching mechanisms during the next 10 years. A means to decrease the threshold and supply voltage and, therefore minimizing power dissipation, is to employ devices which exhibit a steeper slope than the MOSFET limit of 60 mV/dec at room temperature. The Tunnel FET promises steep turn-on characteristics and low leakage currents as compared to MOSFETs which make it attractive for low-power operation. A great deal of work over the past years has been done to boost device performance of Tunnel FETs by combining ultimate wrap-gate architectures, incorporation of III/V materials and band engineering for hetero-tunnel junctions. The latter is seen as an ideal route towards achieving high drive currents and steep sub-threshold slopes at low supply voltages. This thesis investigates both Si Tunnel FETs and the route towards heterostructure Tunnel FETs, but also the technological challenges to achieve these device structures. The first part of this work deals with vapor-liquid-solid grown silicon in-situ doped n+-i-p nanowire Tunnel FETs in a lateral geometry, where the influence of the gate dielectric, i.e., SiO2 or HfO2, on device performance is investigated along with the study of low-temperature behavior. The devices having the strongest gate coupling due to the high-κ gate oxide HfO2 are shown to exhibit the best device performance as compared with the SiO2 gate stack. A vertical process for Si FETs is developed and improved to obtain a fully wrap-gate geometry. It is adaptable to different material systems and is the basis for the ongoing work on InAs-on-Si nanowire Tunnel FETs. Improved performance for these heterostructure devices requires in particular high doping concentrations as well as abrupt doping profiles to achieve high tunnel currents. Therefore, the second part focuses on the InAs material system and specifically the study of dopant incorporation. Doping is done in-situ using different precursors during growth. The InAs nanowires are grown in SiO2 mask openings on 〈111〉 Si substrates in a metal-organic vapor phase epitaxy process. The effect of the dopants and growth parameters on radial and vertical growth rates, wire morphology and resistivity is investigated. A method utilizing the measured Seebeck coefficient of the InAs nanowires to extract doping densities without the need of assuming a mobility value is presented. Two other reference methods where I-V characteristics of homo-and heterojunction InAs tunnel diodes are fitted by TCAD simulations confirm this approach. Doping densities ranging from 1·1017 cm−3 to 7.1·1019 cm−3 were achieved which is comparable to the highest doping concentration reported in bulk InAs. Furthermore, single vertical pn+-junctions are fabricated by growing n-type InAs nanowires on p-type InAs substrates, which show high tunnel current densities of 500 kA/cm2 at 0.3 V reverse bias. In the forward direction, negative differential resistance is obtained below 200 K, which is the characteristic feature of an Esaki diode.

EPFL2012

Chargement

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

EPFL2012

EPFL2005

EPFL2004