ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories

Communication systems have been associated with an inherent fault tolerance to hardware reliability issues. Therefore, many publications have studied the impact of such issues on, for example, channel (mostly LDPC) decoders. Since all of these studies are so far only based on simulations, we implement an LDPC decoder in a 28nm technology, specifically to verify the corresponding assumptions and quality metrics. Our measurements indicate a large quality spread across a population of dies, which is not visible when considering an average quality across simulation runs with random fault injection. Such a quality spread is detrimental since in high-volume manufacturing a certain minimum quality must be guaranteed for all accepted dies. The latter is only possible with an ergodic behaviour in which the quality of any faulty die is indicative for the quality of all dies in the population. To alleviate this issue, ErgoDEC provides simple architectural measure to restore an ergodic behaviour in the presence of memory reliability issues. This more stable quality can also be observed in our measurements and can be exploited to further improve the resilience against faulty bits.