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Due to its high parallelism, belief propagation (BP)decoding is amenable to high-throughput applications and thusrepresents a promising solution for the ultra-high peak datarate required by future communication systems. To bridge theperformance gap compared to the widely used successive cancel-lation list (SCL) decoding algorithm, BP list (BPL) decoding forpolar codes extends candidate codeword exploration via multiplepermuted factor graphs (PFGs) to improve the error-correctingperformance of BP decoding. However, it is a significant challengeto design a unified and flexible BPL hardware architecture thatsupports various PFGs and code configurations. In this paper,we present the first VLSI implementation of a BPL decoder forpolar codes that overcomes this implementation challenge with ahardware-friendly algorithm for on-the-fly flexible permutations.First, we introduce a sequential generation (SG) algorithm toobtain a near-optimal PFG set. Additionally, we demonstratethat any permutation can be decomposed into a combination ofmultiple fixed routings, and design a low-complexity permutationnetwork to generate graphs in an on-the-fly fashion. Our BPLdecoder has a low decoding latency by executing decoding andpermutation generation in parallel and supports arbitrary listsizes without area overhead. Experimental results based on 28nmFD-SOI technology show that for length-1024 polar codes witha code rate of one-half, our BPL decoder with 32 PFGs exhibitssimilar error-correcting performance to SCL with a list size of 4and achieves an average throughput of 25.63 Gbps and an areaefficiency of 29.46 Gbps/mm2, which is 1.82xand 4.33xfasterthan the state-of-the-art BP flip and SCL decoders, respectively
Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Yifei Shen, Yuqing Ren, Hassan Harb
Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Andreas Toftegaard Kristensen, Yifei Shen, Yuqing Ren, Chuan Zhang