Publications related to SuperH

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi, Joshua Alexander Harrison Klein

Transformer models have achieved impressive results in various AI scenarios, ranging from vision to natural language processing. However, their computational complexity and their vast number of parameters hinder their implementations on resource-constraine ...

2023

Attention-based domain adaptation for single-stage detectors

Mathieu Salzmann, Vidit Vidit

While domain adaptation has been used to improve the performance of object detectors when the training and test data follow different distributions, previous work has mostly focused on two-stage detectors. This is because their use of region proposals make ...

SPRINGER2022

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Irem Boybat Kara, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein, Abu Sebastian

Analog in-memory computing (AIMC) cores offers significant performance and energy benefits for neural network inference with respect to digital logic (e.g., CPUs). AIMCs accelerate matrix-vector multiplications, which dominate these applications’ run-time. ...

2022

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon

With the spread of cloud services and Internet of Things concept, there is a popularization of machine learning and artificial intelligence based analytics in our everyday life. However, an efficient deployment of these data-intensive services requires per ...

2019

Study of additive manufactured microwave cavities for pulsed optically pumped atomic clock applications

Anja Skrivervik, Emile Jacques de Rijk

Additive manufacturing (AM) of passive microwave components is of high interest for the cost-effective and rapid prototyping or manufacture of devices with complex geometries. Here, we present an experimental study on the properties of recently demonstrate ...

2018

A reconfigurable cryogenic platform for the classical control of quantum processors

Edoardo Charbon, Harald Arjan Robert Homulle, Fabio Sebastiano

The implementation of a classical control infrastructure for large-scale quantum computers is challenging due to the need for integration and processing time, which is constrained by coherence time. We propose a cryogenic reconfigurable platform as the hea ...

2017

Unified prefetching into instruction cache and branch target buffer

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes: tagging a plurality of target buffer entries that belong to branches within a same instruction blo ...

2017

Accelerating Machine Learning with Non-Volatile Memory: exploring device and circuit tradeoffs

Alessandro Fumarola, Severin Sidler

Large arrays of the same nonvolatile memories (NVM) being developed for Storage-Class Memory (SCM) such as Phase Change Memory (PCM) and Resistance RAM (ReRAM) - can also be used in non-Von Neumann neuromorphic computational schemes, with device conductanc ...

Ieee2016

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SuperH

Highly Parallel RTL Simulation

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Attention-based domain adaptation for single-stage detectors

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

Study of additive manufactured microwave cavities for pulsed optically pumped atomic clock applications

A reconfigurable cryogenic platform for the classical control of quantum processors

Unified prefetching into instruction cache and branch target buffer

Accelerating Machine Learning with Non-Volatile Memory: exploring device and circuit tradeoffs

Ensuring Asset Optimization through Ontology-based Modelling of Technical Documentation

Graph Chatbot

Chat with Graph Search

Highly Parallel RTL Simulation

Ensuring Asset Optimization through Ontology-based Modelling of Technical Documentation

Accelerating Machine Learning with Non-Volatile Memory: exploring device and circuit tradeoffs

Unified prefetching into instruction cache and branch target buffer

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

Study of additive manufactured microwave cavities for pulsed optically pumped atomic clock applications

A reconfigurable cryogenic platform for the classical control of quantum processors

ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Attention-based domain adaptation for single-stage detectors