Concept

Logic family

Related publications (176)

Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems

The power efficiency of source-coupled logic (SCL) topology for implementing ultra-low-power and low-activity-rate circuits is investigated. It is shown that in low-activity-rate circuits, where the subthreshold leakage consumption of conventional CMOS cir ...

2009

A 16-bit, 150-μW, 1-kS/s ADC with hybrid incremental and cyclic conversion scheme

Pierre-André Farine, Luca Rossi, Steve Tanner

This paper presents the design, realization and characterization of a new hybrid A/D converter based on a combined incremental and cyclic conversion. The proposed implementation offers a configurable resolution, and permits to share the same hardware for t ...

2009

Pico-Watt Source-Coupled Logic Circuits

Seyed Armin Tajalli, Yusuf Leblebici

This article explores the main tradeoffs in design of subthreshold source-couple logic (STSCL) circuits. It is shown analytically that the bias current of each STSCL gate can be reduced to few pico-amperes with a reliable logic operation. Measurements on d ...

2008

MOS current-mode logic standard cells for high-speed low-noise applications

Stéphane Badel

With the continuous shrinking of devices dimensions in microelectronic circuits, it is becoming extremely desirable to integrate analog circuitry together with complex digital logic blocks. The noise generated by the digital parts in a mixed-signal integra ...

EPFL2008

Initialization Mechanism in Kohonen Neural Network Implemented in CMOS Technology

Rafal Tomasz Dlugosz

An initialization mechanism is presented for Kohonen neural network implemented in CMOS technology. Proper selection of initial values of neurons’ weights has a large influence on speed of the learning algorithm and finally on the quantization error of the ...

2008

Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic

Mihai Adrian Ionescu, Dimitrios Tsamados, Yogesh Singh Chauhan, Christoph Eggimann

An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is based on the depletion approximation and expresses the pull-in voltage, the pull-out voltage, and t ...

2008

Overview of Traffic Signal Operation Policies for Ramp Metering

A ramp metering control algorithm includes typically two distinct components: the (most important) control strategy, which makes real-time decisions on the ramp exit flow to be implemented, and the translation of this decision into specific traffic light s ...

National Academy of Sciences2008

A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

Seyed Armin Tajalli, Yusuf Leblebici, Mohammad Beikahmadi

The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data co ...

NORCHIP2008

A telemetric pressure sensor system for biomedical applications

Philippe Renaud

A new implantable pressure sensor for long-term monitoring of intracranial pressure is presented. The sensor is powered by telemetry and can be interrogated wirelessly. A capacitive pressure transducer, whose capacitance is converted to a frequency-encoded ...

2008

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18um CMOS technology

Seyed Armin Tajalli, Yusuf Leblebici, Zeynep Toprak Deniz, Omer Can Akgun, Thomas Liechti

This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...

IEEE2008

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