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Related publications (97)

The top-down fabrication of a 3D-integrated, fully CMOS-compatible FET biosensor based on vertically stacked SiNWs and FinFETs

Mihai Adrian Ionescu, Montserrat Fernandez-Bolanos Badia, Elizabeth Buitrago Godinez, Sara Rigante

A 3D vertically stacked silicon nanowire (SiNW) and Fin field effect transistor (FET) featuring a high density array (7 or 8 x 20 SiNWs, > 4 Fins vertically stacked) of fully depleted, ultra-thin (SiNWs diameters similar to 15-30 nm, Fin width/height fw si ...

Elsevier2014

METROII: A Design Environment for Cyber-Physical Systems

Alena Simalatsar, Qi Zhu

Cyber-Physical Systems are integrations of computation and physical processes and as such, will be increasingly relevant to industry and people. The complexity of designing CPS resides in their heterogeneity. Heterogeneity manifest itself in modelin ...

2013

An implantable biosensor array for personalized therapy applications

Andrea Cavallini

At present, most of the tests involved in personalized medicine are complex and must be conducted in specialized centers. The development of appropriate, fast and inexpensive diagnostic technologies can encourage medical personnel in performing preventive ...

EPFL2013

Miniature curved artificial compound eyes

Dario Floreano, Ramon Pericet Camara, Michal Karol Dobrzynski, Géraud L'Eplattenier

In most animal species, vision is mediated by compound eyes, which offer lower resolution than vertebrate single-lens eyes, but significantly larger fields of view with negligible distortion and spherical aberration, and high temporal resolution in a tiny ...

National Academy of Sciences2013

Surface tension-driven self-assembly

Massimo Mastrangeli

This chapter reviews the capillary self-assembly (SA) of heterogeneous systems composed by milli- to micrometer-sized building blocks. The representative, though not exhaustive, examples of microsystems presented belong to four main classes: two-dimensiona ...

Springer2013

Die-Stacked DRAM Caches for Servers: Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache

Babak Falsafi, Stavros Volos

Recent research advocates using large die-stacked DRAM caches to break the memory bandwidth wall. Existing DRAM cache designs fall into one of two categories — block-based and page-based. The former organize data in conventional blocks (e.g., 64B), ensurin ...

ACM2013

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

John Richard Thome, Michail Zervas, Yusuf Leblebici, Yassir Madhour, Bruno Michel

Three-dimensional (3D) stacking of integrated circuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconn ...

IEEE2013

Packaging technologies for high temperature control electronics

Peter Ryser, Yusuf Leblebici, Thomas Maeder, Conor Joseph Slater, Radisav Cojbasic

Current low temperature electronics (175°C) for prolonge ...

IMAPS2013

Runtime 3-D Stacked Cache Management for Chip-Multiprocessors

Giovanni De Micheli

These-dimensional (3-D) memory stacking is one of the most promising solutions to memory bandwidth problems in chip multiprocessors. In this work, we propose an efficient runtime 3-D cache management technique which takes advantage of the lower latencies t ...

2013

A 2D/3D image analysis system to track fluorescently labeled structures in rod-shaped cells: application to measure spindle pole asymmetry during mitosis

Michaël Unser, Daniel Sage, Viesturs Simanis, Daniel Andreas Schmitter, Anastasia Chasapi, Ioannis Xenarios

Background: The yeast Schizosaccharomyces pombe is frequently used as a model for studying the cell cycle. The cells are rod-shaped and divide by medial fission. The process of cell division, or cytokinesis, is controlled by a network of signaling proteins ...

Biomed Central Ltd2013

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