Publications related to Package on a package

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Yusuf Leblebici, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos

A novel modular, cost e ffective 3D multi-processor architecture is presented. Auto-configurable and independently testable identical dies are stacked exploiting Through-Silicon-Vias (TSV) technology, allowing to target different market segments by selecti ...

2012

Vertically stacked Si nanostructures for biosensing applications

Mihai Adrian Ionescu, Montserrat Fernandez-Bolanos Badia, Elizabeth Buitrago Godinez

High density (7-10 NW/μm) SiNW arrays of up to 16 nanowires vertically stacked with diameter widths below 20 nm have been successfully fabricated to create highly sensitive 3D FETs for biosensing applications. In order to take advantage of the increased se ...

Elsevier2012

Nonparametric Construction of Multivariate Kernels

Victor Panaretos, Kjell Konis

We propose a nonparametric method for constructing multivariate kernels tuned to the configuration of the sample, for density estimation in R-d, d moderate. The motivation behind the approach is to break down the construction of the kernel into two parts: ...

American Statistical Association2012

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Luca Benini, Federico Angiolini, Subhasish Mitra

Through silicon vias (TSVs) provide an efficient way to support vertical communication among different layers of a vertically stacked chip, enabling scalable 3-D networks-on-chip (NoC) architectures. Unfortunately, low TSV yields significantly impact the f ...

2011

Addressable MEMS slit mask for multi-object spectroscopy based on multi-wafer stacking

Nico de Rooij, Michael David Canonica, Wilfried Noell

MEMS-based programmable slit masks are developed for multi-object spectroscopy in astronomy. Devices with 2048 tiltable micromirrors were fabricated using multiple wafer-level bonding and implemented with individual addressing of each element. ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoC), being a system-level interconnect, can play a major role in achieving low-power SoC designs. In many designs, the cores are grouped in to Voltage Islands (VIs). To reduce the leakage power consumption, an island containing cores tha ...

Springer New York2011

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floorplanner. Our contributions include: (1) a novel multi-objective formulation to cons ...

IEEE Press2011

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Giovanni De Micheli, Shashi Kanth Bobba, Thomas Ernst

3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contac ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Hierarchical Thermal Management Policy for High-Performance 3D Systems with Liquid Cooling

Giovanni De Micheli, David Atienza Alonso, Mohamed Mostafa Sabry Aly, Francesco Zanini

3-Dimensional integrated circuits and systems are expected to be present in electronic products in the short term. We consider specifically 3-D multi-processor systems-onchip (MPSoCs), realized by stacking silicon CMOS chips and interconnecting them by mea ...

2011

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Package on a package

Soudure par interdiffusion dans les systèmes Au-In et In-Ni

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Vertically stacked Si nanostructures for biosensing applications

Nonparametric Construction of Multivariate Kernels

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Addressable MEMS slit mask for multi-object spectroscopy based on multi-wafer stacking

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits

Hierarchical Thermal Management Policy for High-Performance 3D Systems with Liquid Cooling

Graph Chatbot

Chat with Graph Search

Soudure par interdiffusion dans les systèmes Au-In et In-Ni

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Vertically stacked Si nanostructures for biosensing applications

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Nonparametric Construction of Multivariate Kernels

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

Addressable MEMS slit mask for multi-object spectroscopy based on multi-wafer stacking

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Hierarchical Thermal Management Policy for High-Performance 3D Systems with Liquid Cooling

CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits