David Atienza AlonsoDavid Atienza Alonso is an associate professor of EE and director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. He received his MSc and PhD degrees in computer science and engineering from UCM, Spain, and IMEC, Belgium, in 2001 and 2005, respectively. His research interests include system-level design methodologies for multi-processor system-on-chip (MPSoC) servers and edge AI architectures. Dr. Atienza has co-authored more than 350 papers, one book, and 12 patents in these previous areas. He has also received several recognitions and award, among them, the ICCAD 10-Year Retrospective Most Influential Paper Award in 2020, Design Automation Conference (DAC) Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He has also earned two best paper awards at the VLSI-SoC 2009 and CST-HPCS 2012 conference, and five best paper award nominations at the DAC 2013, DATE 2013, WEHA-HPCS 2010, ICCAD 2006, and DAC 2004 conferences. He serves or has served as associate editor of IEEE Trans. on Computers (TC), IEEE Design & Test of Computers (D&T), IEEE Trans. on CAD (T-CAD), IEEE Transactions on Sustainable Computing (T-SUSC), and Elsevier Integration. He was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. He served as President of IEEE CEDA in the period 2018-2019 and was GOLD member of the Board of Governors of IEEE CASS from 2010 to 2012. He is a Distinguished Member of ACM and an IEEE Fellow.
Babak FalsafiBabak is a Professor in the School of Computer and Communication Sciences and the founding director of the EcoCloud, an industrial/academic consortium at EPFL investigating scalable data-centric technologies. He has made numerous contributions to computer system design and evaluation including a scalable multiprocessor architecture which was prototyped by Sun Microsystems (now Oracle), snoop filters and memory streaming technologies that are incorporated into IBM BlueGene/P and Q and ARM cores, and computer system performance evaluation methodologies that have been in use by AMD, HP and Google PerKit . He has shown that hardware memory consistency models are neither necessary (in the 90's) nor sufficient (a decade later) to achieve high performance in multiprocessor systems. These results eventually led to fence speculation in modern microprocessors. His latest work on workload-optimized server processors laid the foundation for the first generation of Cavium ARM server CPUs, ThunderX. He is a recipient of an NSF CAREER award, IBM Faculty Partnership Awards, and an Alfred P. Sloan Research Fellowship. He is a fellow of IEEE and ACM.
Paolo IennePaolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.
Willy ZwaenepoelWilly Zwaenepoel received his B.S. from the University of Gent, Belgium in 1979, and his M.S. and Ph.D. from Stanford University in 1980 and 1984, respectively. In September 2002, he joined EPFL. He was Dean of the School of Computer and Communications Sciences at EPFL from 2002 to 2011. Before joining EPFL, Willy Zwaenepoel was on the faculty at Rice University, where he was the Karl F. Hasselmann Professor of Computer Science and Electrical and Computer Engineering.
He was elected Fellow of the IEEE in 1998, and Fellow of the ACM in 2000. In 2000 he received the Rice University Graduate Student Association Teaching and Mentoring Award. In 2007 he received the IEEE Tsutomu Kanai award. He was elected to the European Academy in 2009. He won best paper awards at SigComm 1984, OSDI 1999, Usenix 2000, Usenix 2006 and Eurosys 2007. He was program chair of OSDI in 1996 and Eurosys in 2006, and general chair of Mobisys in 2004. He was also an Associate Editor of the IEEE Transactions on Parallel and Distributed Systems from 1998 to 2002.
Willy Zwaenepoel has worked in a variety of aspects of operating and distributed systems, including microkernels, fault tolerance, parallel scientific computing on clusters of workstations, clusters for web services, mobile computing, database replication and virtualization. He is most well known for his work on the Treadmarks distributed shared memory system, which was licensed to Intel and became the basis for Intels OpenMP cluster product. His work on high-performance software for network I/O led to the creation of iMimic Networking, Inc, which he led from 2000 to 2005. His current interests include large-scale data stores and software testing. Most recently, his work in software testing led to the creation of BugBuster, a startup based in Lausanne.
Andreas Peter BurgAndreas Burg was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree in 2000 from the Swiss Federal Institute of Technology (ETH) Zurich, Zurich, Switzerland. He then joined the Integrated Systems Laboratory of ETH Zurich, from where he graduated with the Dr. sc. techn. degree in 2006.
In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his doctoral studies, he was an intern with Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he held positions as postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. In January 2009, he joined ETH Zurich as SNF Assistant Professor and as head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory.
In January 2011, he became a Tenure Track Assistant Professor at the Ecole Polytechnique Federale de Lausanne (EPFL) where he is leading the Telecommunications Circuits Laboratory in the School of Engineering. In June 2018 he was promoted to the role of a Tenured Associate Professor.
In 2000, Mr. Burg received the Willi Studer Award and the ETH Medal for his diploma and his diploma thesis, respectively. Mr. Burg was also awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, he received a 4-years grant from the Swiss National Science Foundation (SNF) for an SNF Assistant Professorship. In his professional career, Mr. Burg was involved in the development of more than 25 ASICs. He is a member of the IEEE and of the European Association for Signal Processing (EURASIP).
Research interests and expertise
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Circuits and systems for telecommunications (wireless and wired)
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Prototyping and silicon implementation of new communication technologies
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Development of communication algorithms and optimization for hardware implementation
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Low-power VLSI signal processing for communications and other applications
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Digital integrated circuits
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Circuits for image and video processing
Ties Jan Henderikus KluterSince January 2011:
Teaching digital systems at the Swiss Federal Institute of Technology, Lausanne Switzerland
Since August 2009:
Teaching responsible for digital systems at the university of applied science of Bern, Bienne Switzerland
2003-2010:
Ph.D. candidate at the Swiss Federal Institute of Technology, Lausanne Switzerland
2002-2003:
Product development team leader in the infotainment group of Agere Systems, Nieuwegein The Netherlands.
1997-2003:
Design Engineer in the design services group of Dedris Embedded Algorithms/Frontier Design BV./Adelante Technologies, Tiel The Netherlands
1996-1997:
Assistant R&D at the faculty of computer controlled systems and computer techniques University of Twente, Enschede The Netherlands
1992-1996:
MSc. education at the Technical University of Twente, Enschede The Netherlands
1988-1992:
Bc. edudation at the Higher Technical School of Groningen, Groningen The Netherlands
Mathias Josef PayerMathias Payer is a security researcher and professor at the EPFL school of computer and communication sciences (IC), leading the HexHive group. His research focuses on protecting applications in the presence of vulnerabilities, with a focus on memory corruption and type violations. He is interested in software security, system security, binary exploitation, effective mitigations, fault isolation/privilege separation, strong sanitization, and software testing (fuzzing) using a combination of binary analysis and compiler-based techniques. More details are available in his CV.
