Are you an EPFL student looking for a semester project?

Work with us on data science and visualisation projects, and deploy your project as an app on top of GraphSearch.

Person

Ties Jan Henderikus Kluter

Since January 2011:

Teaching digital systems at the Swiss Federal Institute of Technology, Lausanne Switzerland

Since August 2009:

Teaching responsible for digital systems at the university of applied science of Bern, Bienne Switzerland

2003-2010:

Ph.D. candidate at the Swiss Federal Institute of Technology, Lausanne Switzerland

2002-2003:

Product development team leader in the infotainment group of Agere Systems, Nieuwegein The Netherlands.

1997-2003:

Design Engineer in the design services group of Dedris Embedded Algorithms/Frontier Design BV./Adelante Technologies, Tiel The Netherlands

1996-1997:

Assistant R&D at the faculty of computer controlled systems and computer techniques University of Twente, Enschede The Netherlands

1992-1996:

MSc. education at the Technical University of Twente, Enschede The Netherlands

1988-1992:

Bc. edudation at the Higher Technical School of Groningen, Groningen The Netherlands

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Related units

Courses taught by this person

Related research domains

Related publications

People doing similar research

Biography

Since January 2011:

Teaching digital systems at the Swiss Federal Institute of Technology, Lausanne Switzerland

Since August 2009:

Teaching responsible for digital systems at the university of applied science of Bern, Bienne Switzerland

2003-2010:

Ph.D. candidate at the Swiss Federal Institute of Technology, Lausanne Switzerland

2002-2003:

Product development team leader in the infotainment group of Agere Systems, Nieuwegein The Netherlands.

1997-2003:

Design Engineer in the design services group of Dedris Embedded Algorithms/Frontier Design BV./Adelante Technologies, Tiel The Netherlands

1996-1997:

Assistant R&D at the faculty of computer controlled systems and computer techniques University of Twente, Enschede The Netherlands

1992-1996:

MSc. education at the Technical University of Twente, Enschede The Netherlands

1988-1992:

Bc. edudation at the Higher Technical School of Groningen, Groningen The Netherlands

Official source

About this result

Related units (4)

Related units

Courses taught by this person (1)

Courses taught by this person

Related research domains (6)

Related research domains

Related publications (15)

Related publications

People doing similar research (124)

People doing similar research

CPU cache

A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster m

Advanced Vector Extensions

Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and Advanced Micro Devices (AMD). They were proposed by Intel in March 2008 and

Cache coherence

In computer architecture, cache coherence is the uniformity of shared resource data that ends up stored in multiple local caches. When clients in a system maintain caches of a common memory resource

CS-173: Digital system design

The goal is to familiarize the students with the hardware components of computing systems, and to teach the modern methods of analysis and synthesis of combinational and sequential systems, with the assistance of high-level languages such as VHDL.

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Philip Brisk, Samuel Burri, Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter

Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading data from the processor pipeline. AVS creates coherence and consistence problems with the data cache. Although a hardware coherence protocol could solve the problem, this approach is costly for a single-processor system. As a low-cost alternative, we introduce Virtual Ways, which ensures coherence through a reduced form of inclusion between the data cache and AVS. Virtual Ways achieve higher performance and lower energy consumption than using a hardware coherence protocol.

Assoc Computing Machinery2014

, , ,

Way Stealing is a simple architectural modification to a cache-based processor that increases the data bandwidth to and from application-specific instruction set extensions (ISEs), which increase performance and reduce energy consumption. Way Stealing offers higher bandwidth than interfacing the ISEs the processor's register file, and eliminates the need to allocate separate memories called architecturally visible storage (AVS) that are dedicated to the ISEs, and to ensure coherence between the AVS memories and the processor's data cache. Our results show that Way Stealing is competitive in terms of performance and energy consumption with other techniques that use AVS memories in conjunction with a data cache.

Institute of Electrical and Electronics Engineers2014

Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors

Edoardo Charbon, Claudio Favi, Ties Jan Henderikus Kluter, Christian Mester

We propose a technique to localize computation in Instruction Set Extensions (ISEs) that are clocked at very high speed with respect to the processor. In order to save power, data to and from Custom Instruction Units (CIUs) is synchronized via an optical signal that is detected through a Single-Photon Avalanche Diode (SPAD) capable of timing uncertainties as low as 50 picoseconds. The CIUs comprise a free-standing local oscillator serving a computing area of a few tens of square micrometers, thus resulting in extremely reduced power dissipations, since the distribution of a high frequency clock over long distances is avoided. This approach is based on the globally asynchronous locally synchronous concept, whereby the granularity of the local domains is reduced to a minimum, thus enabling extremely high local clock frequencies and low power, while minimizing substrate noise injection and intra-chip interference. Thanks to this approach we can free ourself from expensive synchronization techniques such as FIFOs, delays, or flip-flop based synchronizers by creating fixed synchronization points in time where data can be exchanged. The paradigm is demonstrated on a chip designed and fabricated in a standard 90nm CMOS technology. A full characterization demonstrates the suitability of the approach.

2012