Microarchitecture | EPFL Graph Search

In computer science and computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA) is implemented in a particular processor. A given ISA may be implemented with different microarchitectures; implementations may vary due to different goals of a given design or due to shifts in technology. Computer architecture is the combination of microarchitecture and instruction set architecture. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the instructions, execution model, processor registers, address and data formats among other things. The microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represente

Micro-mechanics of 3D architectured metals synthesized by electrodeposition

Maxime Alain Baptiste Mieszala

Cellular metallic materials have emerged as a new promising class of materials due to their lightweight porous structures and advanced multi-functional properties. Originally limited to random metallic foams, modern lithography techniques have enabled the design of hierarchical cellular structures with tailored mechanical properties. In addition, the mechanical properties of micro-cellular metals can be further improved by taking advantage of the properties of metals, which are size-sensitive at this length scale. It is therefore expected that the combination of architectured cellular designs with size effects in metals would result in materials with unprecedented mechanical properties. The present thesis aims at investigating and understanding the influence of size effects on the mechanical properties of three-dimensional micro-architectured metal structures synthesized using advanced lithography techniques and electrochemical deposition of metals. Electrodeposited copper films with engineered microstructures and nickel-based hierarchical micro-cellular structures were manufactured and tested under uniaxial loading conditions. The results of the tests were used to evaluate the contribution of the size effects and/or architecture to the change in mechanical properties and deformation behavior. The influence of the intrinsic size effect was first demonstrated in electrodeposited pure copper films. Using nanoscale twins to engineer the grain boundaries, it was possible to produce copper films with high strength and significantly tune the mechanical properties by adjusting the twin orientation. The combination of size effects was then investigated for two types of micro-architecture. The first type of metal micro-architecture was obtained by plating nanocrystalline Ni inside a self-assembled colloidal crystal of microspheres in order to produce a regular inverse opal. The second type was fabricated by metallizing a 3D polymer template produced by 3D laser lithography with an amorphous NiB coating. Results show that there is a complex interaction between the characteristic external dimension and cellular structure. For regular Ni inverse opal, there is a complex interaction between the ligament size and the grain size which defines the overall strength of cellular metals. In the case of hybrid NiB/polymer structures, the brittle-to-ductile transition in the amorphous NiB coating and the architecture effect are coupled. By varying the NiB thickness and the architecture geometry, it is possible to control the deformation mechanism from global buckling to brittle failure and to tune the energy absorption characteristics of the micro-architectures. Through these case studies, it was demonstrated that the combination of grain boundary engineering, sub-micron geometrical features and overall architecture can yield 3D metallic micro-architectures, which are both light and strong and have tailored mechanical properties. The mechanical properties of some of these materials exceed the properties of either of the parent materials. Therefore, the constitutive mechanical laws for porous metals should be modified to account for these three effects all together. The results confirmed the potential of our experimental approach and provide a practical way to extend the material property-space.

EPFL2018

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Hassan Harb

This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of 10(-3).

SPRINGER2022

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

Andreas Peter Burg, Anupam Chattopadhyay, Jeremy Hugues-Felix Constantin, Georgios Karakonstantis

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

2015

Micro-mechanics of 3D architectured metals synthesized by electrodeposition

Maxime Alain Baptiste Mieszala

EPFL2018