Concept

One-instruction set computer

Related publications (40)

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Accurate and complexity-effective spatial pattern prediction

Babak Falsafi

Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixed cache line sizes to balance the exploitation of spatial and temporal locality, a ...

2004

Dynamically Reducing Pressure on the Physical Register File through Simple Register Sharing (Best Paper Award)

Using register renaming and physical registers, modern microprocessors eliminate false data dependences from reuse of the instruction set defined registers (logical registers). High performance processors that have longer pipelines and a greater capacity t ...

2004

Introduction of Local Memory Elements in Synthesis of Instruction Set Extensions

Paolo Ienne

Automatic generation of Instruction Set Extensions (ISEs), executed on a custom processing unit or a coprocessor, is an important step towards processor customization. A typical goal of a manual designer is to combine a large number of atomic instructions ...

2003

A virtual model for simulation and design of architectures in MPEG-4 audio and multimedia context

Giorgio Zoia

Research in multimedia for consumer electronics is dominated by the problem of incredibly short times-to-market, that means fast complexity estimations and fast design of new architectures. On one side more and more sophisticated and flexible applications ...

EPFL2001

Selective, accurate, and timely self-invalidation using last-touch prediction

Babak Falsafi

Communication in cache-coherent distributed shared memory (DSM) often requires invalidating (or writing back) cached copies of a memory block, incurring high overheads. This paper proposes Last-Touch Predictors (LTPs) that learn and predict the “last touch ...

2000

Specifying the Semantics of Machine Instructions

Shane Sendall

Computer architecture manuals describe the instruction set of the machine and the semantics of those instructions by a combination of natural language and ISP (Instruction Set Processor) descriptions. The syntax of the instructions in assembly is well defi ...

IEEE Computer Society1998

Factoring integers using SIMD sieves

Arjen Lenstra

We describe a single-instruction multiple data (SIMD) implementation of the multiple polynomial quadratic sieve integer factoring algorithm. On a 16K MasPar massively parallel computer, the implementation can factor 100 digit integers in a few days. Its mo ...

1994

Massively parallel computing and factoring

Arjen Lenstra

Knowing the limits of factoring capabilities is important for various reasons. A favorite example is the security of factoring based cryptosystems, which is based on our inability to solve the factoring problem. There are also cryptosystems, however, which ...

1992

Evaluation of the SPUR Lisp Architecture

James Richard Larus

The SPUR microprocessor has a 40-bit tagged architecture designed to improve its performance for Lisp programs. Although SPUR includes just a small set of enhancements to the Berkeley RISC-II architecture, simulation results show that with a 150-ns cycle t ...

ACM1986

A Comparison of Microcode, Assembly Code, and High-Level Languages on the VAX-11 and RISC I

James Richard Larus

This paper compares the performance of three implementations of simplified pattern matching instruction. The fastest version was microprogrammed on a VAX-11/750, the next fastest was written for a Reduced Instruction Set. Computer (RISC I) developed at Ber ...

ACM1982