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An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

DC Performance Results Versus Assessment of ITER Main Busbar NbTi Conductors

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

Serially concatenated coding for broadcasting S-UMTS applications

Serially concatenated coding for broadcasting S-UMTS applications

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

DC Performance Results Versus Assessment of ITER Main Busbar NbTi Conductors

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services