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The advent of multicore CPUs has led to renewed interest in software routers built from commodity PC hardware. However, fully exploiting the parallelism due to multiple cores requires the ability to efficiently parallelize the delivery of packets to cores. ...
This dissertation deals with the design of practical erasure codes for storage systems. Hardware and logical disk failures are a common source of system failures that may lead to data loss. Nevertheless, it is predicted that spinning disks would remain the ...
3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The red ...
Growing core counts have highlighted the need for scalable on-chip coherence mechanisms. The increase in the number of on-chip cores exposes the energy and area costs of scaling the directories. Duplicate-tag based directories require highly associative st ...
Transmission electron microscopy (TEM) and X-ray diffraction (XRD) were used to study the porous and non-porous alpha-tricalcium phosphate (alpha-Ca-3(PO4)(2), alpha-TCP) prepared through a sintering procedure at 1200-1400 degrees C of beta-tricalcium phos ...
This paper presents a new approach to GPS/INS data acquisition and synchronization for the most popular sensors adopted by the mapping industry for direct-georeferencing; the tactical-grade FOG/silicon-based inertial sensors and generic dual frequency GPS ...