Concept

Reconfigurable computing

Related publications (376)

Integrated Microfluidic Power Generation and Cooling for Bright Silicon MPSoCs

David Atienza Alonso, Arvind Raj Mahankali Sridhar, Mohamed Mostafa Sabry Aly, Bruno Michel

The soaring demand for computing power in our digital information age has produced as collateral undesirable effect a surge in power consumption and heat density for computing servers. Accordingly, 30-40% of the energy consumed in state-of-the-art servers ...

IEEE/ACM Press2014

Low Power and Scalable Many-Core Architecture for Big-Data Stream Computing

David Atienza Alonso, Karim Kanoun, Martino Ruggiero

In the last years the process of examining large amounts of different types of data, or Big-Data, in an effort to uncover hidden patterns or unknown correlations has become a major need in our society. In this context, stream mining applications are now wi ...

IEEE Press2014

Pattern-Based FPGA Logic Block and Clustering Algorithm

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

In classical FPGA, LUTs and DFFs are pre-packed into BLEs and then BLEs are grouped into logic blocks. We propose a novel logic block architecture with fast combinational paths between LUTs, called pattern-based logic blocks. A new clustering algorithm is ...

IEEE2014

RCMP: Enabling Efficient Recomputation Based Failure Resilience for Big Data Analytics

Florin Dinu

Data replication, the main failure resilience strategy used for big data analytics jobs, can be unnecessarily inefficient. It can cause serious performance degradation when applied to intermediate job outputs in multi-job computations. For instance, for I/ ...

2014

Scalable Simulation Methodologies for Many-Core Heterogeneous Systems

Shivani Raghav

With increasing complexity and performance demands of emerging compute-intensive data-parallel workloads, many-core computing systems are becoming a popular trend in computer design. Fast and scalable simulation methods are needed to make meaningful predic ...

EPFL2014

Network-on-chip using request and reply trees for low-latency processor-memory communication

Babak Falsafi, Boris Robert Grot

A Network-On-Chip (NOC) organization comprises a die having a cache area and a core area, a plurality of core tiles arranged in the core area in a plurality of subsets, at least one cache memory bank arranged in the cache area, whereby the at least one cac ...

2014

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

For more than four decades, Complementary Metal-Oxide- Semiconductor (CMOS) Field Effect Transistors (FETs) have been the baseline technology for implementing digital computation systems. CMOS transistors natively implement Not-AND ...

2014

Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

Streaming applications describe a broad class of computing algorithms in areas such as signal processing, media coding and compression, cryptography, video analytics, network touting and packet processing and many others. For many of these applications, pr ...

Ieee2014

Coarse grain clock gating of streaming applications in programmable logic implementations

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

IEEE2014

Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Michele De Marchi

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity ...

Institute of Electrical and Electronics Engineers2014

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