Publications related to High-level synthesis

Generating Configurable Hardware from Parallel Patterns

In recent years the computing landscape has seen an increasing shift towards specialized accelerators. Field programmable gate arrays (FPGAs) are particularly promising for the implementation of these accelerators, as they offer significant performance and ...

Assoc Computing Machinery2016

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis

Mathias Soeken, Anupam Chattopadhyay

Latest quantum technologies promise realization of extremely large circuits, whereas, reversible logic synthesis, the key automation step for quantum computing suffers from scalability bottleneck. Sealability can be achieved with Decision Diagram (DD)-base ...

ACM/IEEE2016

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Paolo Ienne, Andrew James Becker, Ryan Charles Kastner, Wei Hu

Secure hardware design is a challenging task that goes far beyond ensuring functional correctness. Important design properties such as non-interference cannot be verified on functional circuit models due to the lack of essential information (e.g., sensitiv ...

Assoc Computing Machinery2016

Near-Infrared High-Resolution Real-Time Omnidirectional Imaging Platform for Drone Detection

Yusuf Leblebici, Vladan Popovic

Recent technological advancements in hardware systems have made higher quality cameras. State of the art panoramic systems use them to produce videos with a resolution of 9000 x 2400 pixels at a rate of 30 frames per second (fps).(1) Many modern applicatio ...

Spie-Int Soc Optical Engineering2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

ACM2016

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang

This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. hi contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...

Ieee2016

Efficient Hardware Design Of Iterative Stencil Loops

David Atienza Alonso, Ivan Beretta, Alessandro Antonio Nacci

A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Review of Advances in Neural Networks: Neural Design Technology Stack

Yusuf Leblebici, Stanislaw Andrzej Wozniak

This review provides a high-level synthesis of significant recent advances in artificial neural network research, as well as multi-disciplinary concepts connected to the far-reaching goal of obtaining intelligent systems. We assume that a global outlook of ...

Elsevier2016

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High-level synthesis

Generating Configurable Hardware from Parallel Patterns

SyReC: A hardware description language for the specification and synthesis of reversible circuits

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Near-Infrared High-Resolution Real-Time Omnidirectional Imaging Platform for Drone Detection

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

Efficient Hardware Design Of Iterative Stencil Loops

Review of Advances in Neural Networks: Neural Design Technology Stack

Deductive Synthesis and Repair

Graph Chatbot

Chat with Graph Search

Near-Infrared High-Resolution Real-Time Omnidirectional Imaging Platform for Drone Detection

Review of Advances in Neural Networks: Neural Design Technology Stack

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

SyReC: A hardware description language for the specification and synthesis of reversible circuits

Efficient Hardware Design Of Iterative Stencil Loops

Generating Configurable Hardware from Parallel Patterns

Deductive Synthesis and Repair

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance