Related publications (5)

Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL.As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and s ...
EPFL2024

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...
EPFL2021

Limitations of Proximity Lithography Printing

Krishnaparvathy Puthankovilakam

Photolithography is one of the earliest technologies used to transfer patterns to a substrate. It is also known as optical lithography since it uses light to transfer the pattern. The main exposure techniques exist in the industry are projection printing, ...
EPFL2017

OCTOPUS: Efficient Query Execution on Dynamic Mesh Datasets

Anastasia Ailamaki, Henry Markram, Felix Schürmann, Thomas Heinis, Farhan Tauheed

Scientists in many disciplines use spatial mesh models to study physical phenomena. Simulating natural phenomena by changing meshes over time helps to understand and predict future behavior of the phenomena. The higher the precision of the mesh models, the ...
2014

A standard CMOS multi-channel single-chip receiver for multi-gigabit optical data communications

Paul Victor Georges Muller

As dictated by ongoing technology scaling and the advent of multi-core systems, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput. However, the available bandwidth of the input/output ( ...
EPFL2006

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