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Related publications (31)

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Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

Michail Zervas, Yusuf Leblebici, Alessandro Cevrero, Yüksel Temiz, Giulia Beanato, Panagiotis Athanasopoulos, Paolo Giovannini

An innovative modular 3-D stacked multi-processor architecture is presented. The platform is composed of completely identical stacked dies connected together by through-silicon-vias (TSVs). Each die features four 32-bit embedded processors and associated m ...

2012

3D Integration Technology for Lab-on-a-Chip Applications

Yüksel Temiz

This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...

EPFL2012

A CMOS Compatible Chip-to-Chip 3D Integration Platform

Carlotta Guiducci, Michail Zervas, Yusuf Leblebici, Yüksel Temiz

In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-lev ...

IEEE2012

Bringing Virtualization to the x86 Architecture with the Original VMware Workstation

Edouard Bugnion

This article describes the historical context, technical challenges, and main implementation techniques used by VMware Workstation to bring virtualization to the x86 architecture in 1999. Although virtual machine monitors (VMMs) had been around for decades ...

Association for Computing Machinery2012

We report on a system to control the emitted wavelength of a laser independently from its pump conditions. To illustrate the concept, it is applied to III-V microdisk lasers fabricated on a CMOS pilot line for application to multicolored optical interconne ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Subthreshold logic can dramatically reduce energy consumption, if the increased circuit delay is of secondary importance. To gain widespread adoption of this design technique (where V-dd < V-th), one of the important consideration is to improve the energy ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Ahmed Yasir Dogan

This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist. The single-core architecture is composed of a processing core (PC), an instruction m ...

Springer-Verlag Heidelberg2011

Simulation of High-Performance Memory Allocators

David Atienza Alonso, José Luis Risco Martin

Elsevier2011

We study online scheduling on m uniform machines, where m - 1 of them have a reference speed 1 and the last one a speed s with 0

Springer US2011

Ambipolar silicon nanowire FETs with stenciled sub-µm metal gate

Giovanni De Micheli, Jürgen Brugger, Andreea Veronica Savu, Davide Sacchetto, Yusuf Leblebici

A fully CMOS compatible fabrication flow using low temperature a-Si LPCVD and stencil lithography has been developed and proved suitable for SiNW FinFETs having ambipolar conductance. The stencil mask has been demonstrated to be a real option for sub-micro ...

2010