Concept

GlobalFoundries

Related publications (187)

Comparison of Different Precision Pseudo Resistor Realizations in the DC-Feedback of Capacitive Transimpedance Amplifiers

In this paper, three different pseudo resistor (PR) realizations are compared regarding their noise and linearity performance within the DC feedback loop of an integrator-differentiator transimpedance amplifier (I-D-TIA). Thanks to its intrinsic shot noise ...

IEEE2019

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Andreas Peter Burg, Robert Giterman, Cosimo Aprile, Yusuf Leblebici, Andrea Bonetti, Jonathan Emmanuel D Narinx, Nicolas Claude Frigerio

Logic-compatible gain-cell embedded DRAM (GC-eDRAM) is an emerging alternative to conventional SRAM for memory-dominated system-on-chip (SoC) designs due to its high-density, low-power, and two-ported operation. Although GCs have a limited data retention t ...

IEEE2019

First Near-Ultraviolet- and Blue-Enhanced Backside-Illuminated Single-Photon Avalanche Diode Based on Standard SOI CMOS Technology

Edoardo Charbon, Claudio Bruschini, Myung Jae Lee

We present the world's first backside-illuminated (BSI) single-photon avalanche diode (SPAD) based on standard silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology. This SPAD achieves a good dark count rate (DCR) after backs ...

2019

Voltage References for the Ultra-Wide Temperature Range from 4.2 K to 300 K in 40-nm CMOS

Edoardo Charbon, Fabio Sebastiano

This paper presents a family of voltage references in standard 40-nm CMOS that exploits the temperature dependence of dynamic-threshold MOS, NMOS and PMOS transistors in weak inversion to enable operation over the ultra-wide temperature range from 4.2 K to ...

IEEE2019

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Elmira Shahrabi, Yusuf Leblebici, Tugba Demirci

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...

ELSEVIER SCIENCE BV2019

A 30-frames/s, 252 x 144 SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming

Edoardo Charbon, Ivan Michel Antolovic, Chunmin Zhang, Scott Anthony Lindner, Juan Mata Pavia, Martin Wolf

A 252 x 144 single-photon avalanche diode (SPAD) pixel sensor, called Ocelot, is reported for light detection and ranging (LiDAR). The sensor, fabricated in the 180-nm CMOS technology, features 1728 12-bit time-to-digital converters (TDCs) with 48.8-ps res ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Exploration of Negative Capacitance Devices and Technologies

Ali Saeidi

Conventional device scaling has been the main guiding principle of the MOS device engineering over these past years. However, this aggressive scaling would be eventually limited due to the inability to remove the heat generated by MOSFET devices. The power ...

EPFL2019

Multi-Objective System-Level Management of Modern Green Data Centers

Ali Pahlevan

In our modern society, the average citizen has turned into a daily cloud user. Despite being virtually transparent for the user, internet services require data centers behind the scenes. Data centers burn several megawatts of power and their electricity bi ...

EPFL2019

Non-destructive piezoelectric characterisation of Sc doped aluminium nitride thin films at wafer level

Paul Muralt, Stefan Mertin, Clemens Benedict Nyffeler, Andrea Mazzalai

Scandium doped aluminium nitride (ScAlN) gained much attention during last years, since its piezoelectric response is much enlarged as compared to pure AlN films. Above 30% Sc the films are of high interest for piezoMEMS sensing and actuation, ultrasound g ...

IEEE2019

Leveraging wafer-level manufacturing process limitations to increase large scale fused silica microlens array uniformity

Toralf Scharf, Wilfried Noell, Raoul Kirner, Jeremy Béguelin

The wafer-level production of Fused Silica microlens arrays is limited by systematic process non-uniformities. The common molten resist-reflow process with subsequent dry-etching allows for manufacturing of microlens arrays on 200 mm wafers. A thorough pro ...

SPIE-INT SOC OPTICAL ENGINEERING2019

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