Concept

Instruction pipelining

Related publications (117)

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

From A to E: Analyzing TPC’s OLTP Benchmarks -- The obsolete, the ubiquitous, the unexplored

Anastasia Ailamaki, Pinar Tözün, Ippokratis Pandis, Ilknur Cansu Kaynak, Dorde Jevdic

Introduced in 2007, TPC-E is the most recently standardized OLTP benchmark by TPC. Even though TPC-E has already been around for six years, it has not gained the popularity of its predecessor TPC-C: all the published results for TPC-E use a single database ...

2013

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

Ahmed Yasir Dogan

According to the World Health Organization, lifestyle-related diseases, e.g., cardiovascular diseases are the major cause of mortality worldwide. An accurate and continuous medical supervision is highly required for diagnosis and treatment of such diseases ...

EPFL2013

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

Giovanni De Micheli, Andreas Peter Burg, Davide Sacchetto, Pierre-Emmanuel Julien Marc Gaillardon, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...

2013

Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems

David Atienza Alonso, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Martino Ruggiero, Ahmed Yasir Dogan

Personal health monitoring systems can offer a cost-effective solution for human healthcare. To extend the lifetime of health monitoring systems, we propose a near-threshold ultra-low- power multi-core architecture featuring low-power cores, yet capable of ...

ACM and IEEE Press2012

Reducing OLTP Instruction Misses With Thread Migration

Anastasia Ailamaki, Pinar Tözün

During an instruction miss a processor is unable to fetch instructions. The more frequent instruction misses are the less able a modern processor is to find useful work to do and thus performance suffers. Online transaction processing (OLTP) suffers from h ...

2012

Low-power processor architecture exploration for online biomedical signal analysis

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

In this study, the authors explore sequential and parallel processing architectures, utilising a custom ultra-low-power (ULP) processing core, to extend the lifetime of health monitoring systems, where slow biosignal events and highly parallel computations ...

Inst Engineering Technology-Iet2012

Power-Efficient Pipelined Analog-to-Digital Converter Architectures for Advanced CMOS Technologies

Among different analog-to-digital converter (ADC) architectures pipelined ADCs are the most suited for medium sampling frequencies (50-300MSPS) and medium resolutions, i.e. 8 to 14 bits. Having the lowest figure-of-merit (FOM) in its bandwidth and resoluti ...

EPFL2012

Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL

Marco Mattavelli, Ab Al Hadi Bin Ab Rahman, Anatoly Prihozhy

This paper describes a pipeline synthesis and optimization technique that increases data throughput of FPGA-based system using minimum pipeline resources. The technique is applied on \CAL dataflow language, and designed based on relations, matrices and gra ...

Hindawi Publishing Corporation2011

An ultra high-speed, mixed-signal emulator for solving power system dynamic equations

Maher Kayal, Laurent Fabre, Ira Nagel, Fabrizio Lo Conte, Guillaume Olivier Lanz

This paper focuses on a new pipelined processing unit architecture dedicated to mixed-signal power system emulation. Prior research in this field has proven that analog emulation overcomes the speed limits of numerical simulators with reliable accuracy. Th ...

IEEE2011

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