Publications related to Reduced instruction set computer

Laws of Order: Expensive Synchronization in Concurrent Algorithms Cannot be Eliminated

Building correct and efﬁcient concurrent algorithms is known to be a difﬁcult problem of fundamental importance. To achieve ef- ﬁciency, designers try to remove unnecessary and costly synchro- nization. However, not only is this manual trial-and-error proc ...

2011

Simulation of High-Performance Memory Allocators

David Atienza Alonso, José Luis Risco Martin

This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist. The single-core architecture is composed of a processing core (PC), an instruction m ...

Elsevier2011

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

David Atienza Alonso, Andreas Peter Burg, Luca Benini, Ahmed Yasir Dogan

Springer-Verlag Heidelberg2011

GPGPU Accelerated Parallel and Fast Simulation of Thousand-core Platforms.

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, performance (and power) evaluation of th ...

2011

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

The multicore revolution and the ever-increasing complexity of computing systems is dramatically changing system design, analysis and programming of computing platforms. Future architectures will feature hundreds to thousands of simple processors and on-ch ...

IEEE/ACM Press2011

An FPGA-based processing pipeline for high definition stereo video

Andreas Peter Burg

This paper presents a real-time processing platform for high definition stereo video. The system is capable to process stereo-video streams at resolutions up to 1920x1080 at 30 frames per second (1080p30). In the hybrid FPGA-GPU-CPU system, a high-density ...

Hindawi Publishing Corporation2011

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoC), being a system-level interconnect, can play a major role in achieving low-power SoC designs. In many designs, the cores are grouped in to Voltage Islands (VIs). To reduce the leakage power consumption, an island containing cores tha ...

Springer New York2011

Student mini-kernel project based on an FPGA board

André Schiper, Zarko Milosevic, Omid Shahmirzadi

The paper describes a mini-kernel project in the context of a Concurrent Programming course. The goal of the project is to implement Java monitors and interrupt handling. The platform for the project is an FPGA board developed initially at EPFL for Compute ...

Association for Computing Machinery2011

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Reduced instruction set computer

Laws of Order: Expensive Synchronization in Concurrent Algorithms Cannot be Eliminated

Simulation of High-Performance Memory Allocators

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

GPGPU Accelerated Parallel and Fast Simulation of Thousand-core Platforms.

Single-Photon Techniques for Standard CMOS Digital ICs

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-core Platforms

An FPGA-based processing pipeline for high definition stereo video

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Formal Analysis of SystemC Designs in Process Algebra

Student mini-kernel project based on an FPGA board

Graph Chatbot

Chat with Graph Search

Laws of Order: Expensive Synchronization in Concurrent Algorithms Cannot be Eliminated

GPGPU-Accelerated Parallel and Fast Simulation of Thousand-core Platforms

Simulation of High-Performance Memory Allocators

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

Single-Photon Techniques for Standard CMOS Digital ICs

Student mini-kernel project based on an FPGA board

GPGPU Accelerated Parallel and Fast Simulation of Thousand-core Platforms.

An FPGA-based processing pipeline for high definition stereo video

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Formal Analysis of SystemC Designs in Process Algebra