Concept

Reduced instruction set computer

Related publications (181)

Fast, quasi-optimal, and pipelined instruction-set extensions

Paolo Ienne, Philip Brisk, Ajay Kumar Verma

Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, the AFUs must satisfy certain constraints in terms of read and write ports betw ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

A microprocessor having at least one application specific functional unit and method to design same

Paolo Ienne

Customisable embedded processors that are available on the market make it possible for designers to speed up execution of applications by using Application-specific Functional Units (AFUs), implementing Instruction-Set Extensions (ISEs). Furthermore, techn ...

2008

Temporal instruction fetch streaming

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough to capture the application, library, and OS instruction working sets of these wo ...

2008

Flexible hardware acceleration for instruction-grain program monitoring

Babak Falsafi, Evangelos Vlachos

Instruction-grain program monitoring tools, which check and analyze executing programs at the granularity of individual instructions, are invaluable for quickly detecting bugs and security attacks and then limiting their damage (via containment and/or reco ...

2008

Joint Hardware-Software Leakage Minimization Approach for the Register File of VLIW Embedded Architectures

Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo

New applications demand very high processing power when run on embedded systems. Very Long Instruction Word (VLIW) architectures have emerged as a promising alternative to provide such processing capabilities under the given energy budget. However, in this ...

2008

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures

Giovanni De Micheli, David Atienza Alonso, Luca Benini

As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can seriously impact system performance and reliability. Thermal balancing policies base ...

2008

IFS-Modeling for Feasible Freeform Timber Constructions

Yves Weinand, Ivo Stotz, Gilles Gouaty

Within the last years, architectural design has shown great interest in the design of new and complex geometries, commonly known as 'free-form' architecture. The lack of constructive feasibility of the designed architectural objects led us to consider disc ...

2008

Two challenges in embedded systems design: predictability and robustness

I discuss two main challenges in embedded systems design: the challenge to build predictable systems, and that to build robust systems. I suggest how predictability can be formalized as a form of determinism, and robustness as a form of continuity. ...

2008

Deep-submicron embedded processor architectures for high-performance, low-cost and low-power

Sylvain Aguirre

Because the market has an insatiable appetite for new functionality, performance is becoming an increasingly important factor. The telecommunication and network domains are especially touched by this phenomenon but they are not the only ones. For instance, ...

EPFL2007

VLSI implementation of a lattice-reduction algorithm for multi-antenna broadcast precoding

Andreas Peter Burg

This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme is based on Brun's algorithm for finding integer relations. We analyze its high-level ar ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2007

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