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Power system dynamic simulators can be classified according to multiple criteria, including speed, precision, cost and modularity (topology, characteristics and model). Existing simulators are based on time-consuming numeric algorithms, which provide very ...
The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT
Institute of Electrical and Electronics Engineers2014
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Manycore chips are emerging as the architecture of choice to provide power efficiency and improve performance, while riding Moore’s Law. In these architectures, on-chip interconnects play a pivotal role in ensuring power and performance scalability. As sup ...
2012
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The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories and pipeline registers, which typically cannot be power-gated during sleep periods as they need to retain data and prog ...
2013
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Firsts results on particle detection using a novel silicon pixel detector are presented. The sensor consists of an array of 48 square pixels with 380 μm pitch based on a n-i-p hydrogenated amorphous silicon (a-Si:H) film deposited on top of a VLSI chip. Th ...
2004
Digital signal processing with filter banks, that is filtering a single signal with several filters and subsequent subsampling (or the converse, that is multiplexing), is an important subject with numerous applications (sub-band coding, transmultiplexing). ...
This paper proposes SC++lite, a sequentially consistent system that relaxes memory order speculatively to bridge the performance gap among memory consistency models. Prior proposals to speculatively relax memory order require large custom on-chip storage t ...
