Publications related to Instruction set simulator

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Samuel Burri, Philip Brisk

Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading da ...

Assoc Computing Machinery2014

Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture

Andreas Peter Burg, Jeremy Hugues-Felix Constantin

In this paper, we investigate the benefit of instruction set extensions for software implementations of all five SHA-3 candidates. To this end, we start from optimized assembly code for a common 16-bit microcontroller instruction set architecture. By thems ...

Cryptology ePrint Archive2012

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Andreas Peter Burg, Jeremy Hugues-Felix Constantin

In this paper, we investigate the benefits of instruction set extensions (ISEs) on a 16-bit microcontroller architecture for software implementations of cryptographic hash functions, using the example of the five SHA-3 final round candidates. We identify t ...

Ieee2012

GPGPU Accelerated Parallel and Fast Simulation of Thousand-core Platforms.

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Future architectures will feature hundreds to thousands of simple processors and on-chip memories connected through a network-on-chip. Architectural simulators will remain primary tools for design space exploration, performance (and power) evaluation of th ...

2011

Circuit Level Modeling Methodology of Parasitic Substrate Current Injection from a High-Voltage H-bridge at High Temperature

Maher Kayal, Jean-Michel Sallese, Fabrizio Lo Conte

In this paper, a modeling methodology is validated based on an enhanced model of the diode, that we have developed to simulate substrate current coupling mechanisms on a typical H -bridge structure. An equivalent schematic based on an enhanced model of the ...

2011

Comparison of Gradient Estimation Methods for Real-time Optimization

Dominique Bonvin, Grégory François

Various real-time optimization techniques proceed by controlling the gradient to zero. These methods primarily differ in the way the gradient is estimated. This paper compares various gradient estimation methods. It is argued that methods with model-based ...

Elsevier2011

Modeling methodology of high-voltage substrate minority and majority carrier injections

Maher Kayal, Jean-Michel Sallese, Fabrizio Lo Conte

This paper presents a modeling methodology for substrate current coupling mechanisms. An enhanced model of the diode ensuring continuity of minority carriers is used to build an equivalent schematic, accounting for minority and majority carrier propagation ...

2010

Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands

Yusuf Onur Koçberber, Ilknur Cansu Kaynak

In contemporary superscalar microprocessors, issue queue is a considerable energy dissipating component due its complex scheduling logic. In addition to the energy dissipated for scheduling activities, read and write lines of the issue queue entries are al ...

2010

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Instruction set simulator

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Efficient Modelling and Simulation Methodology for the Design of Heterogeneous Mixed-Signal Systems on Chip

GPGPU Accelerated Parallel and Fast Simulation of Thousand-core Platforms.

Circuit Level Modeling Methodology of Parasitic Substrate Current Injection from a High-Voltage H-bridge at High Temperature

Comparison of Gradient Estimation Methods for Real-time Optimization

Modeling methodology of high-voltage substrate minority and majority carrier injections

Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands

An Abstract Interpretation-Based Framework for Control Flow Reconstruction from Binaries

Graph Chatbot

Chat with Graph Search

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

Efficient Modelling and Simulation Methodology for the Design of Heterogeneous Mixed-Signal Systems on Chip

GPGPU Accelerated Parallel and Fast Simulation of Thousand-core Platforms.

Comparison of Gradient Estimation Methods for Real-time Optimization

Circuit Level Modeling Methodology of Parasitic Substrate Current Injection from a High-Voltage H-bridge at High Temperature

Reducing the Energy Dissipation of the Issue Queue by Exploiting Narrow Immediate Operands

An Abstract Interpretation-Based Framework for Control Flow Reconstruction from Binaries

Modeling methodology of high-voltage substrate minority and majority carrier injections