Publications related to Bit slicing

Horizontal side-channel full key recovery on ephemeral SIKE

Natacha Yolande Emmanuel Marie Linard de Guertechin, Aymeric Genet, Novak Kaluderovic

This paper describes the first practical single-trace side-channel power analysis of SIKE. The attack exploits the nature of elliptic curve point addition formulas which require the same function to be executed multiple times. We target the three point lad ...

2021

Six shades lighter: a bit-serial implementation of the AES family

Subhadeep Banik, Muhammed Fatih Balli, Sergio Roldán Lombardía

Recently, cryptographic literature has seen new block cipher designs such as PRESENT, GIFT or SKINNY that aim to be more lightweight than the current standard, i.e., AES. Even though AES family of block ciphers were designed two decades ago, they still rem ...

2021

The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits

Andrea Felice Caforio, Subhadeep Banik, Muhammed Fatih Balli

The bit-sliding paper of Jean et al. (CHES 2017) showed that the smallest-size circuit for SPN based block ciphers such as AES, SKINNY and PRESENT can be achieved via bit-serial implementations. Their technique decreases the bit size of the datapath and na ...

2020

A Dual-Edge Pulsewidth Modulator for Fast Dynamic Response DC-DC Converters

Maher Kayal, Adil Koukab, Giacomo Ripamonti, Stefano Michelis, Federico Faccio

Voltage regulator modules are dc-dc converters that power modern microprocessors. They must exhibit a fast dynamic response, in order to achieve satisfactory regulation performance in spite of the rapid load current variations. The pulsewidth modulator is ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Mihai Adrian Ionescu, Anna Krammer, Teodor Rosca, Josef Andreas Schuler, Wolfgang Amadeus Vitale, Cem Alper, Arnab Biswas, Emanuele Andrea Casu, Qun Zhao

Steep-slope transistors allow to scale down the supply voltage and the energy per computed bit of information as compared to conventional field-effect transistors (FETs), due to their sub-60 mV/decade subthreshold swing at room temperature. Currently pursu ...

Nature Publishing Group2017

1024-Channel Single 5W FPGA Towards High-quality Portable 3D Ultrasound Platform

Jean-Philippe Thiran, Giovanni De Micheli, Marcel Arditi, Aya Mohamed Naguib Ahmed Ibrahim, Ahmet Caner Yüzügüler

Volumetric Ultrasound (US) imaging is an emerging tech- nology for medical US applications. Typically, US imaging is 2D, where a number of vibrating elements, arranged in an array, are used to scan 2D cross-sections of the human body. In volumetric US a ma ...

2017

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Real-Time Neural Signals Decoding onto Off-the-Shelf DSP Processors for Neuroprosthetic Applications

Silvestro Micera, Stanisa Raspopovic

The control of upper limb neuroprostheses through the peripheral nervous system (PNS) can allow restoring motor functions in amputees. At present, the important aspect of the realtime implementation of neural decoding algorithms on embedded systems has bee ...

Ieee-Inst Electrical Electronics Engineers Inc2016

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Bit slicing

Horizontal side-channel full key recovery on ephemeral SIKE

Six shades lighter: a bit-serial implementation of the AES family

The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits

Enhanced-performance integrated Resonant Switched-Capacitor and Buck DC-DC converters for application in extreme radiation and magnetic field environments

A Dual-Edge Pulsewidth Modulator for Fast Dynamic Response DC-DC Converters

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

1024-Channel Single 5W FPGA Towards High-quality Portable 3D Ultrasound Platform

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Real-Time Neural Signals Decoding onto Off-the-Shelf DSP Processors for Neuroprosthetic Applications

Balancing family with a successful career in neuroscience

Graph Chatbot

Chat with Graph Search

Enhanced-performance integrated Resonant Switched-Capacitor and Buck DC-DC converters for application in extreme radiation and magnetic field environments

1024-Channel Single 5W FPGA Towards High-quality Portable 3D Ultrasound Platform

Real-Time Neural Signals Decoding onto Off-the-Shelf DSP Processors for Neuroprosthetic Applications

A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor

Balancing family with a successful career in neuroscience

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Horizontal side-channel full key recovery on ephemeral SIKE

Six shades lighter: a bit-serial implementation of the AES family

The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits

A Dual-Edge Pulsewidth Modulator for Fast Dynamic Response DC-DC Converters