Concept

Explicit parallelism

Related publications (16)

A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication

David Atienza Alonso, Giovanni Ansaloni, Grégoire Axel Eggermann, Marco Antonio Rios

State-of-the-art Artificial Intelligence (AI) algorithms, such as graph neural networks and recommendation systems, require floating-point computation of very large matrix multiplications over sparse data. Their execution in resource-constrained scenarios, ...

2023

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Jonathan Emmanuel D Narinx

The capability to process high-resolution videos in real-time is becoming more important in a wide variety of applications such as autonomous vehicles, virtual reality or intelligent surveillance systems. The high-accuracy and complex video processing algo ...

EPFL2019

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Christian Enz, Vincent Frédéric Camus, Alessandro Pezzotta, Jérémy Lucien Maurice Schlachter, Mattia Cacciotti

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an ...

IEEE2018

Scaling and Resilience in Numerical Algorithms for Exascale Computing

Allan Svejstrup Nielsen

The first Petascale supercomputer, the IBM Roadrunner, went online in 2008. Ten years later, the community is now looking ahead to a new generation of Exascale machines. During the decade that has passed, several hundred Petascale capable machines have bee ...

EPFL2018

Towards Real-Time High-Resolution Interferometric Imaging with Bluebild

Sepand Kashani

Rooted in radio-astronomy, the Bluebild algorithm is a paradigm-changing imager to estimate the sky intensity function. However, current imaging pipelines in radio-astronomy are highly-tailored to the CLEAN-family of imagers, and hence lack the flexibility ...

2017

FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages

Nithin George

Field Programmable Gate Arrays (FPGAs) have the unique ability to be configured into application-specific architectures that are well suited to specific computing problems. This enables them to achieve performances and energy efficiencies that outclass oth ...

EPFL2016

Safety, Liveness and Parallelism in Concurrent Computing

Victor Bushkov

The correctness of a shared object, which can be accessed by several processes concurrently, is specified through two different kinds of properties - safety and liveness. When implementing a shared object it is important to specify its correctness in a suc ...

EPFL2015

An explicit dynamics GPU structural solver for thin shell finite elements

Nicola Parolini, Andrea Bartezzaghi

With the availability of user oriented software tools, dedicated architectures, such as the parallel computing platform and programming model CUDA (Compute Unified Device Architecture) released by NVIDIA, one of the main producers of graphics cards, and of ...

Elsevier2015

Transactions Chasing Scalability and Instruction Locality on Multicores

Pinar Tözün

For several decades, online transaction processing (OLTP) has been one of the main server applications that drives innovations in the data management ecosystem, and in turn the database and computer architecture communities. Recent hardware trends oblige s ...

EPFL2014

Limits to high-speed simulations of spiking neural networks using general-purpose computers

Wulfram Gerstner, Friedemann Zenke

To understand how the central nervous system performs computations using recurrent neuronal circuitry, simulations have become an indispensable tool for theoretical neuroscience. To study neuronal circuits and their ability to self-organize, increasing att ...

Frontiers Research Foundation2014

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