Publications related to Xeon Phi

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

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In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

2022

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

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String sorting is an important part of database and MapReduce applications; however, it has not been studied as extensively as sorting of fixed-length keys. Handling variable-length keys in hardware is challenging and it is no surprise that no string sorte ...

IEEE COMPUTER SOC2020

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

Felix Schürmann, James Gonzalo King, Michael Lee Hines, Pramod Shivaji Kumbhar, Aleksandr Ovcharenko, Jérémy Pierre Benoit Fouriaux

The NEURON simulator has been developed over the past three decades and is widely used by neuroscientists to model the electrical activity of neuronal networks. Large network simulation projects using NEURON have supercomputer allocations that individually ...

2019

RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs

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Modern online services come with stringent quality requirements in terms of response time tail latency. Because of their decomposition into fine-grained communicating software layers, a single user request fans out into a plethora of short, μs-scale RPCs, ...

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Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

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This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I-V and G-V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear ons ...

Institute of Electrical and Electronics Engineers2017

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The European Dynamical Exascale Entry Platform (DEEP) is an example of a new type of heterogeneous supercomputing architecture that include both a standard multicore-based "Cluster" used to run less scalable parts of an application, and an Intel MIC-based ...

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Worst-case execution time analysis for many-core architectures with NoC

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The optimal deployment of data streaming applications onto multi-/many-core platform providing real-time guarantees requires to solve the application partitioning and placement, buffer allocation and task mapping and scheduling optimisation problem using t ...

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Xeon Phi

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

GPU-Accelerated Finite Volume Particle Simulation of Free Jet Deviation by Multi-jet Rotating Pelton Runner

RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

Leveraging a Cluster-Booster Architecture for Brain-Scale Simulations

Worst-case execution time analysis for many-core architectures with NoC

Graph Chatbot

Chat with Graph Search

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

CoreNEURON : An Optimized Compute Engine for the NEURON Simulator

Leveraging a Cluster-Booster Architecture for Brain-Scale Simulations

Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms

Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions

Worst-case execution time analysis for many-core architectures with NoC

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

GPU-Accelerated Finite Volume Particle Simulation of Free Jet Deviation by Multi-jet Rotating Pelton Runner

RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs