Publications related to Lookup table

LUT-Based Optimization For ASIC Design Flow

Giovanni De Micheli, Luca Gaetano Amarù, Eleonora Testa

In this paper, we develop a new LUT-based optimization flow tailored for the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the literal/AIG cost of LUT-nodes. We extend traditional Boolean methods to simplify and re-shape LUT-netw ...

2021

Advanced Functional Decomposition Using Majority and Its Applications

Giovanni De Micheli, Mathias Soeken, Zhufei Chu

Typical operators for the decomposition of Boolean functions in state-of-the-art algorithms are AND, exclusive-OR (XOR), and the 2-to-1 multiplexer (MUX). We propose a logic decomposition algorithm that uses the majority-of-three (MAJ) operation. Such a de ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis

Giovanni De Micheli, Mathias Soeken, Heinz Riener, Winston Jason Haaswijk

The paper presents a generalization of DAG-aware AIG rewriting for k-feasible Boolean networks, whose nodes are k-input lookup tables (k-LUTs). We introduce a high-effort DAG-aware rewriting algorithm, called cut rewriting, which uses exact synthesis to co ...

IEEE2019

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Circuits naturally exhibit recurring patterns of local interconnect. Hardening those patterns when designing Field Programmable Gate Array (FPGA) clusters can both eliminate slow programmable connections from the critical path and remove the need for trans ...

IEEE2019

Interleaving with Coroutines: A Practical Approach for Robust Index Joins

Anastasia Ailamaki, Georgios Psaropoulos

Index join performance is determined by the efficiency of the lookup operation on the involved index. Although database indexes are highly optimized to leverage processor caches, main memory accesses inevitably increase lookup runtime when the index outsiz ...

VLDB Endowment Inc.2017

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware

Alexandre Schmid, Yusuf Leblebici, Abdulkadir Akin, Halima Najibi, Luis Manuel Gaemperle

Real-time disparity estimation requires real-time rectification which involves solving the models of lens distortions, image translations and rotations. Low complexity look-up-table based rectification algorithms usually require an external memory to store ...

Springer-Verlag Berlin2015

Asynchronous memory access chaining

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber

In-memory databases rely on pointer-intensive data structures to quickly locate data in memory. A single lookup operation in such data structures often exhibits long-latency memory stalls due to dependent pointer dereferences. Hiding the memory latency by ...

2015

A Case for Heterogeneous Technology-Mapping: Soft versus Hard Multiplexers

Paolo Ienne, Madhura Purnaprajna

Lookup table-based FPGAs offer flexibility but compromise on performance, as compared to custom CMOS implementations. This paper explores the idea of minimising this performance gap by using fixed, fine-grained, non-programmable logic structures in place o ...

Ieee2013

Compressed look-up-table based real-time rectification hardware

Alexandre Schmid, Yusuf Leblebici, Abdulkadir Akin, Ipek Baz, Luis Manuel Gaemperle

Stereo image rectification is a pre-processing step of disparity estimation intended to remove image distortions and to enable stereo matching along an epipolar line. A real-time disparity estimation system needs to perform real-time rectification which re ...

2013

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Lookup table

LUT-Based Optimization For ASIC Design Flow

Advanced Functional Decomposition Using Majority and Its Applications

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Interleaving with Coroutines: A Practical Approach for Robust Index Joins

Efficient Decentralized Visual Place Recognition From Full-Image Descriptors

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware

Asynchronous memory access chaining

A Case for Heterogeneous Technology-Mapping: Soft versus Hard Multiplexers

Compressed look-up-table based real-time rectification hardware

Graph Chatbot

Chat with Graph Search

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware

Compressed look-up-table based real-time rectification hardware

LUT-Based Optimization For ASIC Design Flow

Advanced Functional Decomposition Using Majority and Its Applications

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis

Asynchronous memory access chaining

A Case for Heterogeneous Technology-Mapping: Soft versus Hard Multiplexers

Interleaving with Coroutines: A Practical Approach for Robust Index Joins

Efficient Decentralized Visual Place Recognition From Full-Image Descriptors