Alexandre Schmid

Alexandre Schmid received the M.Sc. degree in microengineering and the Ph.D. degree in electrical engineering from the Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, in 1994 and 2000, respectively. Since 1994, he has been with the EPFL, working with the Integrated Systems Laboratory as a Research and Teaching Assistant, and with the Electronics Laboratories as a Postdoctoral Fellow. In 2002, he was a Senior Research Associate with the Microelectronic Systems Laboratory, where he has been conducting research in the fields of bioelectronic interfaces and implantable biomedical electronics, nonconventional signal processing and neuromorphic hardware, and reliability of nanoelectronic devices, and also teaches with the Microengineering and Electrical Engineering Departments of EPFL. Since 2011, he is a Maître d'Enseignement et de Recherche (MER) Faculty Member with EPFL. He is a coauthor of two books, Reliability of Nanoscale Circuits and Systems, Methodologies and Circuit Architectures, Springer, 2011, and Wireless Cortical Implantable Systems, Springer, 2013, and a coeditor of one book, as well as over 100 articles published in journals and conferences.

Dr. Schmid has served as the General Chair of the Fourth International Conference on Nano-Networks in 2009 and has been serving as an Associate Editor of the Institute of Electrical, Information, and Communication Engineers Electronics Express since 2009.

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A system is a group of interacting or interrelated elements that act according to a set of rules to form a unified whole. A system, surrounded and influenced by its environment, is described by its

An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor materi

In mathematics (in particular, functional analysis), convolution is a mathematical operation on two functions (f and g) that produces a third function (f*g) th

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EE-110: Logic systems (for MT)

Ce cours couvre les fondements des systèmes numériques. Sur la base d'algèbre Booléenne et de circuitscombinatoires et séquentiels incluant les machines d'états finis, les methodes d'analyse et de synthèse de systèmelogiques sont étudiées et appliquée

EE-207: Logic systems (for EL)

Ce cours couvre les fondements des systèmes numériques. Sur la base d'algèbre Booléenne et de circuits combinatoires et séquentiels incluant les machines d'états finis, les methodes d'analyse et de synthèse de système logiques sont étudiées et appliquées.

EE-208: Microcontrollers and digital systems

Microcontrôleurs et conception de systèmes numériques couvre le fonctionnement interne d'un microcontrôleur, des notions de base d'architecture de processeur et de système informatique ainsi que les interfaces de microcontrôleurs, et protocoles de communication série.

A system is a group of interacting or interrelated elements that act according to a set of rules to form a unified whole. A system, surrounded and influenced by its environment, is described by its

An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or a microchip) is a set of electronic circuits on one small flat piece (or "chip") of semiconductor materi

In mathematics (in particular, functional analysis), convolution is a mathematical operation on two functions (f and g) that produces a third function (f*g) th

Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

Keyvan Farhang Razi, Alexandre Schmid

A programmable patient-customized epileptic seizure detector is proposed in this paper to enable neurologists and patients to have constructive interactions with the implantable medical device. The programmability feature is enabled by designing a low-power 32-bit MIPS-based RISC processor which consists of five stages and supports three types of instructions. This work exhibits superiority over the existing seizure detectors since the RISC processor can be programmed by physicians to define different therapy options that are safe and efficient for each patient. Moreover, the patients have the opportunity of adjusting the seizure detection parameters by switching between different therapy options available under the permission of their physicians in order to enhance seizure detection performance. Seizure detection is performed by exploiting widely-used computational complexity-efficient time-domain features in conjunction with a feature ranking unit. The classification task is conducted by three logical functions which are defined to reach specific therapeutic goals such as rapid seizure detection and minimum false positive detections. Patients can dynamically adjust the critical seizure detection parameters such as sensitivity, specificity, and detection delay to make the medical device compatible with their current condition. The proposed programmable seizure detector is implemented on an ALTERA DE10-standard board with a Cyclone V FPGA and tested on 10 patients with 65 seizure events of the SWEC-ETHZ database from the Inselspital Bern which reveals a low dynamic power consumption of 0.78 mW which confirms its compatibility with low-power implantable devices.

IEEE2023

Computation Complexity Reduction Technique for Accurate Seizure Detection Implants

Keyvan Farhang Razi, Alexandre Schmid

An automatic seizure detection method from high-resolution intracranial-EEG (iEEG) signals is presented to minimize the computational complexity and realize real-time accurate seizure detection for biomedical implants. Complex signal processing on a large amount of iEEG signals captured via several electrodes is a crucial impediment in seizure detection when it comes to power consumption and real-time processing. Therefore, a subject-customized channel selection method correlated to a feature ranking unit is proposed to improve the computation efficiency and seizure detection accuracy by reducing the dimension of extracted features as well as the electrode channels. Nine popular time-domain features are extracted and ranked to constitute a customized feature subset. Subsequently, electrode channels are ranked with respect to the top four rank features obtained from the feature ranking unit. Then, the number of channels is optimized to reach the highest detection accuracy. The selected channels are compressed into a single channel to minimize the signal processing computation load. The suggested method is tested on seven patients with 37 seizure events from the SWEC-ETHZ dataset of the Bern University Hospital. The perfect sensitivity of 100%, the specificity of 92.98%, and the mean detection delay of 3.6 sec are achieved which outperform the state-of-the-art. In addition, the computation complexity is remarkably reduced which makes the presented method suitable for low-power real-time biomedical implants.

IEEE2022

Dynamic Probabilistic Pruning: A General Framework for Hardware-Constrained Pruning at Different Granularities

Lizeth Gonzalez Carabarin, Alexandre Schmid

Unstructured neural network pruning algorithms have achieved impressive compression ratios. However, the resulting-typically irregular-sparse matrices hamper efficient hardware implementations, leading to additional memory usage and complex control logic that diminishes the benefits of unstructured pruning. This has spurred structured coarse-grained pruning solutions that prune entire feature maps or even layers, enabling efficient implementation at the expense of reduced flexibility. Here, we propose a flexible new pruning mechanism that facilitates pruning at different granularities (weights, kernels, and feature maps) while retaining efficient memory organization (e.g., pruning exactly k-out-of- n weights for every output neuron or pruning exactly k-out-of-n kernels for every feature map). We refer to this algorithm as dynamic probabilistic pruning (DPP). DPP leverages the Gumbel-softmax relaxation for differentiable k-out-of-n sampling, facilitating end-to-end optimization. We show that DPP achieves competitive compression ratios and classification accuracy when pruning common deep learning models trained on different benchmark datasets for image classification. Relevantly, the dynamic masking of DPP facilitates for joint optimization of pruning and weight quantization in order to even further compress the network, which we show as well. Finally, we propose novel information-theoretic metrics that show the confidence and pruning diversity of pruning masks within a layer.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022