Publications related to ATX | EPFL Graph Search

Methods and systems for power-efficient inductive chip-to-chip communications

Digital information is communicated between stacked integrated circuit devices by inductive coupling between arrays of inductors formed from integrated circuit wiring layers. This can be done using a combination of push-pull drivers, common inductor return ...

2015

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW and 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a ...

2014

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An 8b 1.2GS/s single-channel SAR converter is implemented in 32nm CMOS, achieving 39.3dB SNDR and a FOM of 34fJ/conversion-step. High-speed operation is achieved by converting each sample with two alternating comparators clocked asynchronously and a redund ...

2013

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate clocking for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC sta ...

2013

Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Rashid Iqbal

The impact of supply voltage scaling on the retention time of a 2-transistor (2T) gain-cell (GC) storage array is investigated, in order to enable low-power/low-voltage data storage. The retention time can be increased when scaling down the supply voltage ...

2012

Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes

Mohammad Amin Shokrollahi, Seyed Armin Tajalli, Harm Cronie

In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a sparse signaling code, wherein a codeword is representable as a vector of a plu ...

2012

Modular DC/DC Converter: Comparison of Modulation Methods

Alfred Rufer, Drazen Dujic, Stephan Kenzelmann

This paper presents a bidirectional modular DC/DC converter. It consists of two Modular Multilevel Converters (MMC) linked by a transformer to achieve galvanic isolation. This topology serves as “DC transformer” interfacing low and medium voltage DC grids. ...

2012

Orthogonal differential vector signaling

Mohammad Amin Shokrollahi, Harm Cronie

Using a transformation based at least in part on a non-simple orthogonal or unitary matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmis ...

2011

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ATX

Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication

An Implantable High-Voltage Cortical Stimulator for Post-stroke Rehabilitation Enhancement with High-Current Driving Capacity

Methods and systems for power-efficient inductive chip-to-chip communications

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time

Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes

Modular DC/DC Converter: Comparison of Modulation Methods

Orthogonal differential vector signaling

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Methods and systems for power-efficient inductive chip-to-chip communications

An Implantable High-Voltage Cortical Stimulator for Post-stroke Rehabilitation Enhancement with High-Current Driving Capacity

Modular DC/DC Converter: Comparison of Modulation Methods

Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication

Orthogonal differential vector signaling

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time