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Related publications (39)

Scale-Out Processors

Babak Falsafi, Michael Ferdman, Boris Robert Grot, Yusuf Onur Koçberber, Pejman Lotfi Kamran, Stavros Volos, Javier Picorel Obando, Al Mutaz Adileh

Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by ...

Ieee2012

Spatiotemporal Coherence Tracking

Mohammad Alisafaee

Chip-multiprocessors require a coherence directory to track data sharing and order accesses to the shared data. Scaling coherence directories to support a large number of cores is challenging due to excessive area requirements of the directories. The state ...

2012

Modelling competence-based virtual organisations using the unified enterprise competence modelling language

Naoufel Cheikhrouhou

Virtual organisations are non-conventional structures aiming at sharing the same goals, developing common practices or creating wealth in a collaborative manner. Accordingly, competence issues are important topics to be addressed in order to ensure coheren ...

Taylor & Francis2012

TurboTag: Lookup Filtering to Reduce Coherence Directory Power

Babak Falsafi, Michael Ferdman, Pejman Lotfi Kamran, Daniel Crisan

On-chip coherence directories of today’s multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary lookups when running commercial server and scientific workloads. These workloads have ...

ACM2010

Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures

Anastasia Ailamaki, Babak Falsafi, Michael Ferdman

The growing core counts and caches of modern processors result in data access latency becoming a function of the data's physical location in the cache. Thus, the placement of cache blocks determines the cache's performance. Reactive nonuniform cache archit ...

2010

Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Samuel Burri, Philip Brisk

Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include Architecturally Visible Storage (AVS), compiler-controlled memories accessible exclus ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

MPSoC Design using Application-Specific Architecturally Visible Communication

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Philip Brisk

This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide high-throughput communication for streaming applications. Producer/consumer relationships map poorly onto cache-based MPSo ...

Springer-Verlag2009

Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors

Babak Falsafi

Distributed shared-memory (DSM) multi- processors provide a scalable hardware platform, but lack the necessary redundancy for mainframe-level reliability and availability. Chip-level redundancy in a DSM server faces a key challenge: the increased latency t ...

2009

Rendering massive real-time crowds

Pablo Stanislaw De Heras Ciechomski

This thesis presents how to visualize a large crowd of virtual human characters in real time on a standard issue personal computer. The virtual humans are distributed into rendering fidelities such that the humans closer to the viewer are detailed and expr ...

EPFL2006

Reunion: Complexity-effective multicore redundancy

Babak Falsafi

To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identical instruction streams is challenging because redundant cores operate indepe ...

2006

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